AD9154 datasheet(28/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 28 of 124

STEP 5: DATA LINK LAYER

This section describes how to set up the data link layer of the

SERDES interface. This section deals with SYSREF processing,

setting deterministic latency, and establishing the link.

Table 22. Data Link Layer Settings

Address

Bit No.

Value1

Variable

Description

0x301

Subclass

See the JESD204B

Setup section.

0x304

LMFCDel

See the Link Latency

Setup section.

0x305

LMFCDel

See the Link Latency

section.

0x306

LMFCVar

See the Link Latency

Setup section.

0x307

LMFCVar

See the Link Latency

Setup section.

0x03A

0x01

Set sync mode = one-

shot sync; see the

Syncing LMFC Signals

section for other sync

options.

0x03A

0x81

Enable the sync

machine.

0x03A

0xC1

Arm the sync machine.

SYSREF±

If Subclass = 1, ensure

that at least one

SYSREF± edge is sent

to the device.2

0x308 to

0x30B

XBarVals

If remapping lanes, set

up crossbar; see the

Crossbar Setup section.

0x334

InvLanes

Invert the polarity of

desired logical lanes.

Bit x of InvLanes must

be a 1 for each Logical

Lane x to invert.

0x300

Enable the links.

CheckSum

Mode

See the JESD204B

Setup section.

DualLink

See the JESD204B

Setup section.

[1:0]

EnLinks

EnLinks = 3 if DualLink

= 1 (enables Link 0 and

Link 1); EnLinks = 1 if

DualLink = 0 (enables

Link 0 only).

1 0x denotes a register value that the user must fill in. See the Variable and

Description columns for information on selecting the appropriate register value.

2 Verify that Register 0x03B, Bit 3 reads back 1 after sending at least one

SYSREF± edge to the device to indicate that the LMFC sync machine has

properly locked.

STEP 6: ERROR MONITORING

For JESD204B error monitoring, see the JESD204B Error

Monitoring section. For other error checks, see the Interrupt

Request Operation section.

DAC PLL SETUP

This section explains how to select appropriate LODivMode,

RefDivMode, and BCount in the Step 1: Start Up the DAC

section. These parameters depend on the desired DAC clock

frequency (fDACCLK) and DAC reference clock frequency (fREF).

When using the DAC PLL, the reference clock signal is applied

to the CLK± differential pins, Pin 2 and Pin 3.

Table 23. DAC PLL LODivMode Settings

DAC Frequency Range (MHz)

LODIVMODE,

1500 to 2400

750 to 1500

420 to 750

Table 24. DAC PLL RefDivMode Settings

DAC PLL Reference

Frequency (fREF) (MHz)

Divide by

(RefDivFactor)

REFDIVMODE,

35 to 80

80 to 160

160 to 320

320 to 640

640 to 1000

The VCO frequency (fVCO) is related to the DAC clock

frequency according to the following equation:

fVCO = fDACCLK × 2LODivMode + 1

where 6 GHz  fVCO  12 GHz.

BCount must be between 6 and 127 and is calculated based on

fDACCLK and fREF as follows:

BCount = floor((fDACCLK)/(2 × fREF/RefDivFactor))

where RefDivFactor = 2RefDivMode (see Table 24).

Finally, to finish configuring the DAC PLL, set the VCO control

registers up as described in Table 80 based on the VCO

frequency (fVCO).

For more information on the DAC PLL, see the DAC Input

Clock Configurations section.

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