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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9154 датащи(PDF) 83 Page - Analog Devices |
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AD9154 датащи(HTML) 83 Page - Analog Devices |
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83 / 124 page  Data Sheet AD9154 Rev. C | Page 83 of 124 SYNCOUTx±, SYSREF±, and CLK± Signals The SYNCOUTx± and SYSREF± signals on the AD9154 are low speed LVDS differential signals. Use controlled impedance traces routed with 100 Ω differential impedance and 50 Ω to ground when routing these signals. As with the SERDIN0± to SERDIN7± data pairs, it is important to keep these signals separated from potential noise sources such as high speed digital signals and noisy supplies. Separate the SYNCOUTx± signal from other noisy signals, because noise on the SYNCOUTx± might be interpreted as a request for K characters. It is important to keep similar trace lengths for the CLK± and SYSREF± signals from the clock source to each of the devices on either end of the JESD204B links, see Figure 88. If using a clock chip that can tightly control the phase of CLK± and SYSREF±, the trace length matching requirements are greatly reduced. AD9154 LANE 0 LANE 1 LANE N – 1 LANE N DEVICE CLOCK DEVICE CLOCK SYSREF± SYSREF± SYSREF TRACE LENGTH SYSREF TRACE LENGTH DEVICE CLOCK TRACE LENGTH DEVICE CLOCK TRACE LENGTH Tx DEVICE Rx DEVICE Figure 88. SYSREF± Signal and Device Clock Trace Length |
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