AD9154 datasheet(21/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 21 of 124

THEORY OF OPERATION

The AD9154 is a 16-bit, quad DAC with a SERDES interface.

Figure 2 shows a detailed functional block diagram of the AD9154.

Eight high speed serial lanes carry data into the AD9154.

The clock for the input data is derived from the device clock (as

called out in the JESD204B specification). This device clock can

be sourced with a phase-locked loop (PLL) reference clock used

by the on-chip PLL to generate a DAC clock or a high fidelity

direct external DAC sampling clock. The device can be configured

to operate in one-, two-, four-, or eight-lane modes, depending on

the required input data rate. The quad DAC can be configured as a

dual link device with each JESD204B link providing data for a dual

DAC pair to add application flexibility.

The signal processing datapath of the AD9154 offers four

interpolation modes (1×, 2×, 4×, and 8×) through three half-band

filters. An inverse sinc filter compensates for DAC output sinc roll-

off. A digital inphase and quadrature modulator upcoverts a pair of

DAC input signals to an IF frequency within the first Nyquist

zone of the DAC programmed into an NCO. Gain, phase, dc offset,

and group delay adjustments can programmably predistort the

DAC input signals to improve LO feedthrough and unwanted

sideband cancellation performance of an analog quadrature

modulator following the AD9154 in a transmitter signal chain.

The AD9154 DAC cores provide a differential current output

with a nominal full-scale current of 20 mA. The differential

current outputs are optimized for integration with the Analog

Devices ADRF6720-27 wideband quadrature modulator. The

AD9154 has a mechanism for multichip synchronization, as

well as a mechanism for achieving deterministic latency (latency

locking). The latency for each DAC remains constant from link

establishment to link establishment. The AD9154 makes use of

the JESD204B Subclass 1 SYSREF signal to establish multichip

synchronization.

The various functional blocks and the data interface must be set

up in a specific sequence for proper operation (see the Device

Setup Guide section). This data sheet describes the various

blocks of the AD9154 in detail, including descriptions of the

JESD204B interface, the control parameters, and the various

registers that set up and monitor the device. The recommended

start-up routine reliably sets up the data link.

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