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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9154 датащи(PDF) 8 Page - Analog Devices |
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AD9154 датащи(HTML) 8 Page - Analog Devices |
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8 / 124 page  AD9154 Data Sheet Rev. C | Page 8 of 124 SYSREF TO DAC CLOCK TIMING SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SYSREF Differential swing = 0.4 V, slew rate = 1.3 V/ns Setup Time AC-coupled 89 ps DC-coupled 111 ps Hold Time AC-coupled 105 ps DC-coupled 145 ps Differential swing = 0.7 V, slew rate = 2.28 V/ns Setup Time AC-coupled 71 ps DC-coupled 81 ps Hold Time AC-coupled 97 ps DC-coupled 118 ps Differential swing = 1.0 V, slew rate = 3.26 V/ns Setup Time AC-coupled 58 ps DC-coupled 64 ps Hold Time AC-coupled 92 ps DC-coupled 108 ps DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY Interface, Excluding Transport Layer Delay Buffer 17 PClock1 cycles Interpolation With or without modulation 1× 94 DAC clock cycles 2× 130 DAC clock cycles 4× 250 DAC clock cycles 8× 474 DAC clock cycles Inverse Sinc 17 DAC clock cycles Fine Modulation 20 DAC clock cycles Coarse Modulation fS/8 8 DAC clock cycles fS/4 4 DAC clock cycles Digital Phase Adjust 12 DAC clock cycles Digital Gain Adjust 12 DAC clock cycles Power-Up Time Dual A Only Register 0x011 from 0x60 to 0x00 30 µs Dual B Only Register 0x011 from 0x18 to 0x00 30 µs All DACs Register 0x011 from 0x78 to 0x00 30 µs 1 PClock is the AD9154 internal processing clock running at the JESD204B lane rate ÷ 40. |
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