AD9154 datasheet(68/124 Pages) AD

68 / 124 page

AD9154

Data Sheet

Rev. C | Page 68 of 124

Blanking State Machine (BSM)

The BSM gently ramps data entering the DAC and flushes the

datapath.

On a falling edge of TX_PROTECT (the TXENx signal delayed

by the Tx ENSM), the datapath holds the latest data value and

the digital gain gently ramps from its set value to 0. At the same

time, the datapath is flushed with zeroes.

On a rising edge of TX_PROTECT, the TXENx signal is delayed

by the Tx ENSM; data is allowed to flow through the datapath

again and the digital gain gently ramps the data from 0 up to the

set digital gain.

Both of the above functions are also triggered automatically by

the LMFC sync logic during a rotation to prevent glitching on

the output.

Ramping

The step size to use when ramping gain to 0 or its assigned value

can be controlled via the GAIN_RAMP_DOWN_STEPx registers

(Register 0x142 and Register 0x143) and the GAIN_RAMP_

UP_STEPx registers (Register 0x140 and Register 0x141). These

registers are paged as described in the Dual Paging section.

The current BSM state can be read back as shown in Table 73.

Table 73. Blanking State Machine Ramping Readbacks

Address

Value

Description

0x147[7:6]

0b00

Data is being held at midscale.

0b01

Ramping gain to 0. Data ramping to

midscale.

0b10

Ramping gain to assigned value. Data

ramping to normal amplitude.

0b11

Data at normal amplitude.

Blanking State Machine IRQ

Blanking completion is available as an IRQ event.

Use Register 0x021, Bit 5 to enable blanking completion for DAC

Dual A (DAC0 and DAC1), and then use Register 0x025, Bit 5

to read back its status and reset the IRQ signal.

Use Register 0x022, Bit 5 to enable blanking completion for

DAC Dual B (DAC2 and DAC3),and then use Register 0x026,

Bit 5 to read back its status and reset the IRQ signal.

See the Interrupt Request Operation section for more

information.

PDP OUTx Generation

external PDP OUTx signal. Register 0x11F, Bit 2 can invert the

PDP OUTx signal, By default, PDP OUTx is high when output is

valid. Both of these registers are paged as described in the Dual

Paging section.

Table 74. PDP OUTx Registers

Addr.

Bit No.

Description

0x013

1: PDP block triggers PDP_OUT

1: Tx ENSM triggers PDP_OUT

1: SPI_PROTECT triggers PDP_OUT

Sets SPI_PROTECT

0x11F

Inverts PDP OUTx

DATAPATH PRBS

The datapath PRBS can verify that the AD9154 datapath is

receiving and correctly decoding data. The datapath PRBS verifies

that the JESD204B parameters of the transmitter and receiver

match, the lanes of the receiver are mapped appropriately, lanes

have been appropriately inverted, if necessary, and in general that

the start-up routine has been implemented correctly.

The datapath PRBS is paged as described in the Dual Paging

section. To run the datapath PRBS test, complete the following

steps:

1. Set up the device in the desired operating mode. See the

Device Setup Guide section for details on setting up the

device.

2. Send PRBS7 or PRBS15 data.

3. Write Register 0x14B, Bit 2 = 0 for PRBS7 or 1 for PRBS15.

4. Write Register 0x14B, Bit 1 and Bit 0 = 0b11 to enable and

reset the PRBS test.

5. Write Register 0x14B, Bit 1 and Bit 0 = 0b01 to enable the

PRBS test and release reset.

6. Wait 500 ms.

7. Check the status by checking the IRQ for DAC0 to DAC3

PRBS as described in the Datapath PRBS IRQ section.

8. If there are failures, set Register 0x008 = 0x01 to view the

status of Dual A (DAC0/DAC1). Set Register 0x08 = 0x02

to view the status of Dual B (DAC2/DAC3).

9. Read Register 0x14B, Bit 7 and Bit 6. Bit 6 is 0 if the I DAC

of the selected dual has any errors. Bit 7 is 0 if the Q DAC of

the selected dual has any errors. This must match the IRQ.

10. Read Register 0x14C to read the error count for the I DAC

of the selected dual. Read Register 0x14D to read the error

count for the Q DAC of the selected dual.

Note that the PRBS processes 32 bits at a time, and compares

the 32 new bits to the previous set of 32 bits. It detects (and

reports) only 1 error in every group of 32 bits, so the error

count partly depends on when the errors are seen. For example,

•

Bits: 32 good, 31 good, 1 bad; 32 good (2 errors)

•

Bits: 32 good, 22 good, 10 bad; 32 good (2 errors)

•

Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good

(3 errors)

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