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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9154 датащи(PDF) 52 Page - Analog Devices |
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AD9154 датащи(HTML) 52 Page - Analog Devices |
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52 / 124 page  AD9154 Data Sheet Rev. C | Page 52 of 124 Table 50. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 3 Address Setting Description 0x453 0x01 or 0x81 Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x1: L = 2 lanes per link 0x454 0x03 Register 0x454, Bits[7:0] = 0x03: F = 4 octets per frame 0x455 0x0F or 0x1F Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe 0x456 0x03 Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link 0x457 0x0F Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458, Bits[7:5] =0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per frame 0x45A 0x00 Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0 0x46C 0x03 Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 and Link Lane 1 0x476 0x04 Register 0x476, Bits[7:0] = 0x04: F = 4 octets per frame 0x47D 0x03 Register 0x47D, Bits[7:0] = 0x03: enable Link Lane 0 and Link Lane 1 4 OCTETS PER LANE (F = 4) 16-BIT NIBBLE GROUP (N = 16) 1 SAMPLE PER CONVERTER PER FRAME (S = 1) DAC0 DAC1 DAC2 DAC3 SERIAL JESD204B DATA (L = 2) SAMPLES NOT SPLIT ACROSS LANES (HD = 0) NIBBLE GROUP 0 CONVERTER 0, SAMPLE 0 NIBBLE GROUP 0 D15 ... D0 (0) LANE 0, OCTET 0 LANE 0, OCTET 1 NIBBLE GROUP 1 CONVERTER 1, SAMPLE 0 D15 ... D0 (0) LANE 0, OCTET 2 LANE 0, OCTET 3 NIBBLE GROUP 2 CONVERTER 2, SAMPLE 0 D15 ... D0 (0) LANE 1, OCTET 0 LANE 1, OCTET 1 NIBBLE GROUP 3 CONVERTER 3, SAMPLE 0 D15 ... D0 (0) LANE 1, OCTET 2 LANE 1, OCTET 3 4 CONVERTERS (M = 4) NIBBLE GROUP 1 NIBBLE GROUP 2 NIBBLE GROUP 3 Figure 62. JESD204B Mode 3 Data Deframing Table 51. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 4 Address Setting Description 0x453 0x03 or 0x83 Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x3: L = 4 lanes per link 0x454 0x00 Register 0x454, Bits[7:0] = 0x00: F = 1 octet per frame 0x455 0x0F or 0x1F Register 0x455, Bits[4:0] = 0x0F or 0x1F: K =16 or 32 frames per multiframe 0x456 0x01 Register 0x456, Bits[7:0] = 0x01: M = 2 converters per link 0x457 0x0F Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per frame 0x45A 0x01 Register 0x45A, Bit 7 = 1: HD = 1; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0 0x46C 0x0F Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 3 0x476 0x01 Register 0x476, Bits[7:0] = 0x01: F = 1 octet per frame 0x47D 0x0F Register 0x47D, Bits[7:0] = 0x0F: Enable Link Lane 0 to Link Lane 3 |
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