AD9154 datasheet(65/124 Pages) AD

65 / 124 page

Data Sheet

AD9154

Rev. C | Page 65 of 124

Table 68. I/Q Phase Adjustment Registers

Addr.

Value

Description

0x111[4]

PHASE_ADJ_ENABLE

Set to 1 to enable phase

adjust

0x11C

PHASEADJ[7:0]

LSB phase adjust code

0x11D

PHASEADJ[12:8]

MSB phase adjust code

DC Offset

The dc offset feature individually offsets the data into the I or Q

DACs. This feature cancels LO leakage at the modulator output.

The offset is programmed individually for I and Q as a 16-bit

twos complement number in LSBs, plus a 5-bit twos complement

number in sixteenths of an LSB, as shown in Table 69. DC offset

is paged as described in the Dual Paging section.

−215 ≤ LSBsOffset < 215

−16 ≤ SixteenthsOffset  15

Table 69. DC Offset Registers

Addr.

Value

Description

0x135[0]

DC_OFFSET_ON

Set to 1 to enable dc offset

0x136

LSBSOFFSETI[7:0]

I DAC LSB dc offset code

0x137

LSBSOFFSETI[15:8]

I DAC MSB dc offset code

0x138

LSBSOFFSETQ[7:0]

Q DAC LSB dc offset code

0x139

LSBSOFFSETQ[15:8]

Q DAC MSB dc offset code

0x13A[4:0]

SIXTEENTHSOFFSETI

I DAC sub-LSB dc offset code

0x13B[4:0]

SIXTEENTHSOFFSETQ

Q DAC sub-LSB dc offset code

Coarse Group Delay

Coarse group delay is a global adjustment of the DAC latency,

and it is programmed to identically affect both DACs in an I/Q

signal pair. The coarse group delay range is in +7/−8 steps. Each

step is ½ DAC clock cycle. The default value of 0x8 sets the

delay to zero. This is useful in applications where the user needs

to tune the latency of the DAC path with some accuracy (for

example, in DPD loop delay adjust).

Write the value to COARSE_GROUP_DLY (Register 0x014).

This is paged as described in the Dual Paging section.

Group Delay Compensation

Group delay compensation provides separate delay tunability to

either an I or Q channel within each dual digital signal pair. The

user can delay either the I or Q output to align their quadrature.

Table 70 shows the register settings used for group delay comp-

ensation. The group delay compensation bypass register is located

at Register 0x046. The GROUPDELAYCOMP (Bits[7:0]) values are

binary, and the default value of 0x00 is a delay compensation of

zero. The difference between this mode and the phase adjust mode

is that group delay compensation can correct for delay differences

between the I and Q channels, while phase adjust cannot. Group

delay compensation is paged as described in the Dual Paging

section.

Table 70. Group Delay Compensation Registers

Addr.

Value

Description

0x046

GROUP DELAY

COMP BYPASS

Set to 3 to bypass both I and Q

compensation

0x044

GROUP DELAY

COMP I [7:0]

±85 ps nominal range

0x045

GROUP DELAY

COMP Q [7:0]

±85 ps nominal range

I TO Q SWAP

I_TO_Q (Register 0x111, Bit 0; paged as described in the Dual

Paging section) is a convenience bit that can be set to send the I

datapath to the Q DAC. Note that this swap occurs at the end of

the datapath (after any modulation, digital gain, phase adjust,

and phase offset). If using M = 1 DACs in DualLink mode (as

described in the DAC Power-Down Setup section), set this bit

to direct data to the DAC3 output.

NCO ALIGNMENT

The NCO alignment block phase aligns the NCO output from

multiple converters. Two NCO alignment modes are supported

by the AD9154. The first is a SYSREF± alignment mode that

phase aligns the NCO outputs to the rising edge of a SYSREF±

pulse. The second alignment mode is a data key alignment; when

this mode is enabled, the AD9154 aligns the NCO outputs when a

user specified data pattern arrives at the DAC input. Note that

the NCO alignment is per dual, and is paged as described in the

Dual Paging section.

SYSREF± NCO Alignment

As with the LMFC alignment, in Subclass 1, a SYSREF± pulse

can phase align the NCO outputs of multiple devices in a system

and multiple channels on the same device. Note that in Subclass 0,

this alignment mode can align the NCO outputs within a device to

an internal processing clock edge. No SYSREF± edge is needed

in Subclass 0, but multichip alignment cannot be achieved. The

steps to achieve a SYSREF NCO alignment are as follows:

Set NCOCLRMODE (Register 0x050, Bits[1:0]) = 0b01 for

SYSREF NCO alignment mode.

Set NCOCLRARM to 1 (Register 0x050, Bit 7).

Perform an LMFC alignment to force the NCO phase align

(see the Syncing LMFC Signals section). The phase

alignment occurs on the next SYSREF± edge.

Note that if in one shot sync mode, the LMFC alignment

block must be armed by setting Register 0x03A, Bit 6 = 1.

If in continuous mode or one shot then monitor mode, the

LMFC align block does not need to be armed; the NCO align

automatically trips on the next SYSREF± edge.

Check the alignment status. If NCO phase alignment was

successful, NCOCLRPASS (Register 0x050, Bit 4) = 1. If phase

alignment failed, NCOCLRFAIL (Register 0x050, Bit 3) = 1.

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