AD9154 datasheet(72/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 72 of 124

DAC INPUT CLOCK CONFIGURATIONS

The AD9154 DAC sample clock or device clock (DACCLK) can

be sourced directly through CLK± (Pin 2 and Pin 3) or by using

on-chip clock multiplication with the same CLK± differential

input serving as the reference. Clock multiplying employs the

on-chip DAC PLL that accepts a reference clock operating at a

submultiple of the desired DACCLK rate. The PLL then multiplies

the reference clock up to the desired DACCLK frequency,

which then generates all the clocks within the AD9154.

DRIVING THE CLK± INPUTS

The CLK± differential input is shown in Figure 75. The on-chip

clock receiver has a differential input impedance of 10 kΩ. CLK±

are not terminated on chip; the inputs are self biased to a common-

mode voltage of 600 mV. The inputs can be driven by differential

PECL or LVDS drivers with ac coupling between the clock source

and the receiver. A typical 100 Ω differential board level

termination resistor is placed between the ac coupling

capacitors and the CLK± pins.

CLK+

CLK–

600mV

5kΩ

Figure 75. Clock Receiver Input Simplified Equivalent Circuit

DAC PLL FIXED REGISTER WRITES

To optimize the PLL across all operating conditions, the

following SPI writes are recommended: 0x087 = 0x62, 0x088 =

0xC9, 0x089 = 0x0E, 0x08A = 0x12, 0x08D = 0x7B, 0x1B0 =

0x00, 0x1B5 = 0xC9, 0x1B9 = 0x24, 0x1BC = 0x0D, 0x1BE =

0x02, 0x1BF = 0x8E, 0x1C0 = 0x2A, 0x1C4 = 0x7E, and 0x1C5

= 0x06.

These writes properly set up the DAC PLL, including the loop

filter and the charge pump.

Loop Filter

The RF PLL filter is fully integrated on-chip and is a standard

passive third-order filter with five 4-bit programmable components

(see Figure 76). The C1, C2, C3, R1, and R3 filter components are

programmed in as listed in DAC PLL fixed register writes in the

DAC PLL Fixed Register Writes section to Register 0x087,

FROM CHARGE PUMP

TO VCO

TO VCO LDO

Figure 76. Loop Filter

Charge Pump

The charge pump current is 6-bit programmable variable with a

range of 0.1 mA to 6.4 mA. It is programmed in Register 0x08A,

Bits[5:0] as shown in the DAC PLL Fixed Register Writes section.

The charge pump is automatically calibrated the first time the

DAC PLL is enabled. The charge pump calibration raises Bit 5

of Register 0x084 after it is complete and valid.

DOWN

CHARGE PUMP CURRENT = 0.1mA TO 6.4mA

TO LOOP FILTER

Figure 77. Charge Pump

CONDITION SPECIFIC REGISTER WRITES

Clock Multiplication Relationships

The on-chip PLL clock multiplier circuit can generate the DAC

sample rate clock from a lower frequency reference clock. The PLL

is integrated on chip. The PLL VCO operates over a frequency

range of 6 GHz to 12 GHz. The PLL configuration parameters

must be programmed before the PLL is enabled. Step by step

instructions on how to program the PLL can be found in the

Starting the PLL section. A functional block diagram of the

clock multiplier is shown in Figure 78.

When in use, the clock multiplication circuit generates the DAC

sampling clock from the reference clock (REFCLK) input. The

frequency of the REFCLK (CLK±) input is referred to as fREF.

The REFCLK input is divided by the variable RefDivFactor. Select

the RefDivFactor variable to ensure that the frequency into the

phase frequency detector (PFD) block is between 35 MHz and

80 MHz. The valid values for RefDivFactor are 1, 2, 4, 8, 16, or 32.

Each RefDivFactor maps to the appropriate REFDIVMODE

Table 77. Mapping of RefDivFactor to REFDIVMODE

DAC Reference

Frequency Range (MHz)

Divide by

(RefDivFactor)

REFDIVMODE

Bits[2:0]

35 to 80

80 to 160

160 to 320

320 to 640

640 to 1000

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