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Data Sheet

AD9154

Rev. C | Page 41 of 124

5. If in one-shot mode, arm the sync machine by writing 1 to

SYNCARM (Register 0x03A, Bit 6).

6. If in Subclass 1, ensure that at least one SYSREF± pulse is

sent to the device.

7. Check the status by reading the following bit fields:

a) REF_BUSY (Register 0x03B, Bit 7) = 0 to indicate that

the sync logic is no longer busy.

b) REF_LOCK (Register 0x03B, Bit 3) = 1 to indicate that

the signals are aligned. This bit updates on every

phase check.

c) REF_WLIM (Register 0x03B, Bit 1) = 0 to indicate

that the phase error is not beyond the specified error

window. This bit updates on every phase check.

d) REFROTA (Register 0x03B, Bit 2) = 1 if the phases

were not aligned before the sync and an alignment

occurred, this indicates that a clock alignment occurred.

This bit is sticky and can be cleared only by writing to

the SYNCCLRSTKY control bit (Register 0x03A, Bit 5).

e) REF_TRIP (Register 0x03B, Bit 0) = 1 to indicate

alignment edge received and phase check occurred.

This bit is sticky and can be cleared only by writing to the

SYNCCLRSTKY control bit (Register 0x03A, Bit 5).

Table 40. Sync Processing Modes

Sync Processing

Mode

SYNCMODE (Register 0x03A,

Bits[3:0])

One-shot

0x01

Continuous

0x02

One-shot then monitor

0x09

Table 41. Sync Window Tolerance

Sync Error Window

Tolerance

ERRWINDOW (Register 0x034,

Bits[2:0])

±1/2 DAC clock cycles

0x00

±1 DAC clock cycles

0x01

±2 DAC clock cycles

0x02

±3 DAC clock cycles

0x03

LMFC Sync IRQ

The sync status bits (REFLOCK, REFROTA, REFTRIP, and

REFWLIM) are available as IRQ events.

Use Register 0x021, Bits[3:0] to enable the sync status bits for

DAC Dual A (DAC0 and DAC1), and then use Register 0x025,

Bits[3:0] to read back their statuses and reset the IRQ signals.

Use Register 0x022, Bits[3:0] to enable the sync status bits for

DAC Dual B (DAC2 and DAC3), and then use Register 0x026,

Bits[3:0] read back their statuses and reset the IRQ signals.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout each system. Data traversing from one clock

domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to

nonrepeatable latencies across the link from power cycle to

power cycle with each new link establishment. Section 6 of the

JESD204B specification addresses the issue of deterministic

latency with mechanisms defined as Subclass 1 and Subclass 2.

The AD9154 supports JESD204B Subclass 0 and Subclass 1

operation, but not Subclass 2. Write the subclass to Register 0x301,

Bits[2:0] and once per link to Register 0x458, Bits[7:5].

Subclass 0

This mode does not require any signal on the SYSREF± pins,

which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same LMFC

cycle and the dual DACs must be synchronized to each other.

Minor Subclass 0 Caveats

Because the AD9154 requires an ILAS, the nonmultiple

converter single lane (NMCDA-SL) case from the JESD204A

specification is only supported when using the optional ILAS.

Error reporting using SYNCOUTx± is not supported when

using Subclass 0 with F = 1.

Subclass 1

This mode gives deterministic latency and allows links to be

synced to within ½ a DAC clock period. It requires an external

SYSREF± signal that is accurately phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.

•

The SYSREF± signal distribution skew within the system

must be less than the desired uncertainty.

•

The SYSREF± setup and hold time requirements must be

met for each device in the system.

•

The total latency variation across all lanes, links and

devices must be ≤10 PClock periods. This includes both

variable delays and the variation in fixed delays from lane

to lane, link to link, and device to device in the system.

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