AD9154 datasheet(33/124 Pages) AD

33 / 124 page

Data Sheet

AD9154

Rev. C | Page 33 of 124

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The JESD204B Setup section explains how to select a JESD204B

operating mode. This section presents an overview of the inner

workings of the AD9154 JESD204B receiver implementation.

The AD9154 has eight JESD204B data ports that receive data.

The eight JESD204B ports can be configured as part of a single

JESD204B link or as part of two separate JESD204B links (dual

link mode) that share a single system reference (SYSREF±) and

device clock (CLK±).

The JESD204B hardware protocol stack consists of three layers:

the physical layer, the data link layer, and the transport layer. These

sections of the hardware are described in subsequent sections,

including information for configuring every aspect of the interface.

Figure 41 shows the communication layers implemented in the

AD9154 serial data interface to recover the clock and deserialize,

descramble, and deframe the data before it is sent to the digital

signal processing section of the device.

The physical layer establishes a reliable channel between the

transmitter and the receiver, the data link layer unpacks the data

into frames of octets and descrambles the data, and the transport

layer receives the descrambled JESD204B frames and converts

them to DAC input samples.

A number of JESD204B parameters (L, F, K, M, N, Np, S, and

HD) define how the data is packed and instruct the device on

how to turn the serial data into samples. These parameters are

defined in detail in the Transport Layer section.

Only certain combinations of parameters are supported. Each

supported combination is called a JESD204B operating mode.

In total, there are 10 single link modes supported by the AD9154,

as described in Table 34. In dual link mode, there are six

supported modes, as described in Table 35.

Each of these tables shows the associated clock rates when the

lane rate is 10 Gbps.

For a particular application, the number of converters to use

(M) and the DataRate are known. The LaneRate and number of

lanes (L) can be traded off as follows:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

where LaneRate must be between 1.42 Gbps and 10.64 Gbps.

Achieving and recovering synchronization of the lanes is very

important. To simplify the interface to the transmitter, the AD9154

designates a master synchronization signal for each JESD204B

link. In single link mode, SYNCOUT0± is the master signal for all

lanes; in dual link mode, SYNCOUT0± is the master signal for

Link 0, and SYNCOUT1± is used as the master signal for Link 1.

If is sent to the transmitter via the SYNCOUT signal of the link.

The transmitter stops sending data and instead sends synchron-

ization characters to all lanes in that link until resynchronization

is achieved.

DESERIALIZER

DATA LINK

LAYER

TRANSPORT

LAYER

SERDIN0±

SYSREF±

SERDIN7±

DUAL A I DATA[15:0]

DUAL A Q DATA[15:0]

DUAL B Q DATA[15:0]

DUAL B I DATA[15:0]

DAC

SYNCOUT1±

SYNCOUT0±

PHYSICAL

LAYER

DESERIALIZER

FRAME TO

SAMPLES

QBD/

DESCRAMBLER

Figure 41. Functional Block Diagram of Serial Link Receiver

Table 34. Single Link JESD204B Operating Modes

Mode

Parameter

M (Converter Counts)

L (Lane Counts)

S (Samples per Converter per Frame)

F (Octets per Frame per Lane)

Example Clocks for 10 Gbps Lane Rate

PClock (MHz)

250

Frame Clock (MHz)

1000

500

250

1000

500

250

1000

500

Sample Clock (MHz)

1000

500

250

1000

500

250

1000

500

AD9154 датащи(PDF) 33 Page - Analog Devices

AD9154 датащи(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL