AD9154 datasheet(67/124 Pages) AD

67 / 124 page

Data Sheet

AD9154

Rev. C | Page 67 of 124

FILTER

AND

MODULATION

DIGITAL

GAIN

PDP

PDP_PROTECT

BSM

BSM_PROTECT

Tx_PROTECT

Tx ENSM

DATA

FROM LMFC

SYNC LOGIC

TXENx

DATA TO DACs

PDP_PROTECT_OUT

PROTECT_OUT_INVERT

PROTECT_OUTx

Tx_PROTECT_OUT

SPI_PROTECT_OUT

SPI_PROTECT

PROTECT OUTx GENERATION

Figure 73. Downstream Protection Block Diagram

Table 71. PDP Registers

Addr.

Bit

No.

Value

Description

0x060

[7:0]

PDP_THRESHOLD[7:0]

Power that triggers

PDP_PROTECT.

8 LSBs.

0x061

[4:0]

PDP_THRESHOLD[12:8]

5 MSBs.

0x062

PDP_ENABLE

Set to 1 to enable PDP.

[3:0]

PDP_AVG_TIME

Can be set from 0 to

10. Averages across

2(9 + PDP_AVG_TIME), IQ

sample pairs.

0x063

[7:0]

PDP_POWER[7:0]

If PDP_THRESHOLD is

crossed, this reads

back the maximum

power seen. If not, this

reads back the

instantaneous power.

8 LSBs.

0x064

[4:0]

PDP_POWER[12:8]

5 MSBs.

Power Detection and Protection IRQ

The PDP_PROTECT signal is available as an IRQ event.

Use Register 0x021, Bit 7 to enable PDP_PROTECT for Dual A

(DAC0 and DAC1), and then use Register 0x025, Bit 7 to read

back its status and reset the IRQ signal.

Use Register 0x022, Bit 7 to enable PDP_PROTECT for Dual B

(DAC2 and DAC3), and then use Register 0x026, Bit 7 to read

back its status and reset the IRQ signal.

See the Interrupt Request Operation section for more

information.

Transmit Enable State Machine

The Tx ENSM is a simple block that controls the delay between

the TXENx signal and the TX_PROTECT signal. This signal is

used as an input to the BSM and its inverse can be routed to an

external pin (PDP_OUTx) to turn downstream components on

or off as desired.

The TXENx signal can power down their associated DAC duals. If

DACA_MASK (Register 0x012, Bit 6) = 1, a falling edge of TXENx

causes DAC Dual A (DAC0 and DAC1) to power down. If DACB_

MASK (Register 0x012, Bit 7) = 1, a falling edge of TXENx causes

DAC Dual B (DAC2 and DAC3) to power down. On a rising edge

of TXENx, without DACA_MASK and DACB_MASK enabled,

the output is valid after the BSM settles (see the Blanking State

Machine (BSM) section). If the masks are enabled, an additional

delay is imposed; the output is not valid until the BSM settles

and the DACs fully power on (nominally an additional ~35 µs).

The Tx ENSM is configured as shown in Table 72 and is paged

as described in the Dual Paging section.

Table 72. Tx ENSM Registers

Addr.

Bit No.

Value

Description

0x11F

[7:6]

PA_FALL

Number of fall counters

to use (1 to 2).

[5:4]

PA_RISE

Number of rise counters

to use (0 to 2).

0x121

[7:0]

RISE_COUNT_0

Delay TX_PROTECT rise

from TXENx rising edge

by 32 × RISE_COUNT_0

DAC clock cycles.

0x122

[7:0]

RISE_COUNT_1

Delay TX_PROTECT rise

from TXENx rising edge

by 32 × RISE_COUNT_1

DAC clock cycles.

0x123

[7:0]

FALL_COUNT_0

Delay TX_PROTECT rise

from TXENx rising edge

by 32 × FALL_COUNT_0

DAC clock cycles. Must

be at least 0x12.

0x124

[7:0]

FALL_COUNT_1

Delay TX_PROTECT rise

from TXENx rising edge

by 32 × FALL_COUNT_1

DAC clock cycles.

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