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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9154 датащи(PDF) 49 Page - Analog Devices |
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AD9154 датащи(HTML) 49 Page - Analog Devices |
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49 / 124 page  Data Sheet AD9154 Rev. C | Page 49 of 124 Mode Configuration Maps Table 47 through Table 56 contain the SPI configuration maps for each mode shown in Figure 59 through Figure 67. Figure 59 through Figure 67 show the associated data flow through the deframing process of the JESD204B receiver for each of the modes. Mode 0 to Mode 10 apply to single link operation. Mode 4 to Mode 10 also apply to dual link operation. Register 0x300 must be set accordingly for single or dual link operation. Additional details regarding all the SPI registers can be found in the Register Summary and Register Details sections. Table 47. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 0 Address Setting Description 0x453 0x07 or 0x87 Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x7: L = 8 lanes per link 0x454 0x00 Register 0x454, Bits[7:0] = 0x00: F = 1 octet per frame 0x455 0x1F Register 0x455, Bits[4:0] = 0x1F: K = 32 frames per multiframe 0x456 0x03 Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link 0x457 0x0F Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0xF: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459, Bits[7:5] = 0x1: JESD204B version; Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per frame 0x45A 0x80 Register 0x45A, Bit 7 = 1: HD = 1; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0 0x46C 0xFF Register 0x46C, Bits[7:0] = 0xFF: Deskew Link Lane 0 to Link Lane 7 0x476 0x01 Register 0x476, Bits[7:0] = 0x01: F = 1 octet per frame 0x47D 0xFF Register 0x47D, Bits[7:0] = 0xFF: Enable Link Lane 0 to Link Lane 7 1 OCTET PER LANE (F = 1) 16-BIT NIBBLE GROUP (N = 16) 1 SAMPLE PER CONVERTER PER FRAME (S = 1) DAC0 DAC1 DAC2 DAC3 SERIAL JESD204B DATA (L = 8) SAMPLES SPLIT ACROSS LANES (HD = 1) NIBBLE GROUP 0 CONVERTER 0, SAMPLE 0 D15 ... D0 LANE 0, OCTET 0 LANE 1, OCTET 0 NIBBLE GROUP 1 CONVERTER 1, SAMPLE 0 D15 ... D0 LANE 2, OCTET 0 LANE 3, OCTET 0 NIBBLE GROUP 2 CONVERTER 2, SAMPLE 0 D15 ... D0 LANE 4, OCTET 0 LANE 5, OCTET 0 NIBBLE GROUP 3 CONVERTER 3, SAMPLE 0 D15 ... D0 LANE 6, OCTET 0 LANE 7, OCTET 0 4 CONVERTERS (M = 4) Figure 59. JESD204B Mode 0 Data Deframing |
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