AD9154 datasheet(39/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 39 of 124

Lane FIFO

The FIFOs in front of the crossbar switch and deframer

synchronize the samples sent on the high speed serial data

interface with the deframer clock by adjusting the phase of the

incoming data. The FIFO absorbs timing variations between the

data source and the deframer; this allows up to two PClock

cycles of drift from the transmitter. The FIFO_STATUS_REG_0

and Register 0x30D, respectively) can be monitored to identify

whether the FIFOs are full or empty.

Lane FIFO IRQ

An aggregate lane FIFO error bit is also available as an IRQ

event. Use Register 0x01F[1] to enable the FIFO error bit, and

then use Register 0x023[1] to read back its status and reset the

IRQ signal. See the Interrupt Request Operation section for

more information.

Crossbar Switch

physical lanes (SERDINx±) to logical lanes used by the SERDES

deframers.

Table 39. Crossbar Registers

Address

Bits

Logical Lane

0x308

[2:0]

XBARVAL0

0x308

[5:3]

XBARVAL1

0x309

[2:0]

XBARVAL2

0x309

[5:3]

XBARVAL3

0x30A

[2:0]

XBARVAL4

0x30A

[5:3]

XBARVAL5

0x30B

[2:0]

XBARVAL6

0x30B

[5:3]

XBARVAL7

Write each XBARVALx with the number (x) of the desired

physical lane (SERDINx±) from which to get data. By default,

all logical lanes use the corresponding physical lane as their data

source. For example, by default XBARVALx = 0, so Logical Lane 0

gets data from Physical Lane 0 (SERDIN0±). If instead the user

wants to use SERDIN4± as the source for Logical Lane 0, the user

must write XBARVALx = 4.

Lane Inversion

can ease routing of the SERDINx± signals. For each Logical

Lane x, set Bit x of Register 0x334 to 1 to invert the lane.

Deframers

The AD9154 consists of two quad byte deframers (QBDs). Each

deframer takes in the 8-bit/10-bit encoded data from the

deserializer (via the crossbar switch), decodes it, and descrambles it

into JESD204B frames before passing it to the transport layer to be

converted to DAC samples. The deframer processes four symbols

(or octets) per processing clock (PClock) cycle.

In single link mode, Deframer 0 is used exclusively and Deframer 1

remains inactive. In dual link mode, both QBDs are active and

must be configured separately using the SEL_REG_MAP_1 bit

(Register 0x300[2]) to select the link to be configured. The

DUALLINK bit (Register 0x300[3]) =1 for dual link, or 0 for

single link.

Each deframer uses the JESD204B parameters that the user has

programmed into the register map to identify how the data has

been packed and how to unpack it. The JESD204B parameters

are discussed in detail in the Transport Layer section; many of

the parameters are also needed in the transport layer to convert

JESD204B frames into samples.

Descrambler

The AD9154 provides an optional descrambler block using a

self synchronous descrambler with a polynomial: 1 + x14 + x15.

Enabling data scrambling reduces the spectral peaks produced

when the same data octets repeat from frame to frame. It also

makes the spectrum data independent so that possible

frequency selective effects on the electrical interface do not

cause data dependent errors. Descrambling of the data is

enabled by setting the SCR bit (Register 0x453[7]) to 1.

Syncing LMFC Signals

The first step in guaranteeing synchronization across links and

devices begins with syncing the LMFC signals. Each DAC dual

(DAC Dual A = DAC0/DAC1 and DAC Dual B = DAC2/DAC3)

has its own LMFC signal. In Subclass 0, the LMFC signals for

each of the two links are synchronized to an internal processing

clock. In Subclass 1, all LMFC signals (for all duals and devices)

are synchronized to an external SYSREF signal.

SYSREF Signal

The SYSREF± signal is a differential source synchronous input that

synchronizes the LMFC signals in both the transmitter and receiver

in a JESD204B Subclass 1 system to achieve deterministic latency.

The SYSREF± signal is an active high signal sampled by the

device clock rising edge. It is best practice that the device clock and

the SYSREF± signals be generated by the same source, such as a

device from the AD9516-0, AD9516-1, AD9516-2, AD9516-3,

AD9516-4, and AD9516-5 family of clock generators, so that

the phase alignment between the signals is fixed. When designing

for optimum deterministic latency operation, consider the

timing distribution skew of the SYSREF± signal in a multipoint

link system (multichip).

The AD9154 supports a single pulse or step, or a periodic

SYSREF± signal. The periodicity can be continuous, strobed, or

gapped periodic.

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