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Core Logic Module (Continued)

5.2.10.2 CPU Power Management

The three greatest power consumers in a system are the

display, the hard drive, and the CPU. The power manage-

ment of the first two is relatively straightforward and is dis-

cussed

Section

5.2.10.3

"Peripheral

Power

Management" on page 172.

APM, if available, is used primarily by CPU power manage-

ment since the operating system is most capable of report-

ing the Idle condition. Additional resources provided by the

Core Logic module supplement APM by monitoring exter-

nal activity and power managing the CPU based on the

system demands. The two processes for power managing

the CPU are Suspend Modulation and 3V Suspend.

Suspend Modulation

Suspend Modulation works by asserting and deasserting

the internal SUSP# signal to the GX1 module for config-

urable durations. When SUSP# is asserted to the GX1

module, it enters an Idle state during which time the power

consumption is significantly reduced. Even though the PCI

clock is still running, the GX1 module stops the clocks to its

core when SUSP# is asserted. By modulating SUSP# a

reduced frequency of operation is achieved.

The Suspend Modulation feature works by assuming that

the GX1 module is Idle unless external activity indicates

otherwise. This approach effectively slows down the GX1

module until external activity indicates a need to run at full

speed,

thereby

reducing

power

consumption.

This

approach is the opposite of that taken by most power man-

agement schemes in the industry, which run the system at

full speed until a period of inactivity is detected, and then

slows down. Suspend Modulation, the more aggressive

approach, yields lower power consumption.

Suspend Modulation serves as the primary CPU power

management mechanism when APM is not present. It also

acts as a backup for situations where APM does not cor-

rectly detect an Idle condition in the system.

To provide high-speed performance when needed, SUSP#

modulation is temporarily disabled any time system activity

is detected. When this happens, the GX1 module is

“instantly” converted to full speed for a programmed dura-

tion. System activities in the Core Logic module are

asserted as: any unmasked IRQ, accessing Port 061h, any

asserted SMI, and/or accessing the Video Processor mod-

ule interface.

The graphics controller is integrated in the GX1 module.

Therefore, the indication of video activity is sent to the Core

Logic module via the serial link (see Section 5.2.2 "PSE-

RIAL Interface" on page 152 for more information on serial

link) and is automatically decoded. Video activity is defined

as any access to the VGA register space, the VGA frame

buffer, the graphics accelerator control registers and the

configured graphics frame buffer.

The automatic speedup events (video and IRQ) for Sus-

pend Modulation should be used together with software-

controlled speedup registers for major I/O events such as

any access to the FDC, HDD, or parallel/serial ports, since

these are indications of major system activities. When

major I/O events occur, Suspend Modulation should be

temporarily disabled using the procedures described in the

Power Management registers in the following subsections.

If a bus master (UltraDMA/33, Audio, USB) request occurs,

the GX1 module automatically deasserts SUSPA# and

grants the bus to the requesting bus master. When the bus

master deasserts REQ#, SUSPA# reasserts. This does not

directly affect the Suspend Modulation programming.

Configuring Suspend Modulation: Control of the Sus-

pend Modulation feature is accomplished using the Sus-

pend Modulation and Suspend Configuration registers (F0

Index 94h and 96h, respectively).

The Suspend Configuration register contains the global

power management enable bit, as well as the enables for

the individual activity speedup timers. The global power

management bit must be enabled for Suspend Modulation

and all other power management resources to function.

Bit 0 of the Suspend Configuration register enables Sus-

pend Modulation. Bit 1 controls how SMI events affect Sus-

pend Modulation. In general this bit should be set to 1,

which causes SMIs to disable Suspend Modulation until it

is re-enabled by the SMI handler.

The Suspend Modulation register controls two 8-bit

counters that represent the number of 32 µs intervals that

the internal SUSP# signal is asserted and then deasserted

to the GX1 module. These counters define a ratio which is

the effective frequency of operation of the system while

Suspend Modulation is enabled.

The IRQ and Video Speedup Timer Count registers (F0

Index 8Ch and 8Dh) configure the amount of time which

Suspend Modulation is disabled when the respective

events occur.

SMI Speedup Disable: If the Suspend Modulation feature

is being used for CPU power management, the occurrence

of an SMI disables Suspend Modulation so that the system

operates at full speed while in SMM. There are two meth-

ods used to invoke this via bit 1 of the Suspend Configura-

tion register.

If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer

(F0 Index 8Ch) to temporarily disable Suspend Modu-

lation when an SMI occurs.

If F0 Index 96h[1] = 1: Disable Suspend Modulation

when an SMI occurs until a read to the SMI Speedup

Disable register (F1BAR0+I/O Offset 08h).

The SMI Speedup Disable register prevents VSA software

from entering Suspend Modulation while operating in

SMM. The data read from this register can be ignored. If

the Suspend Modulation feature is disabled, reading this

I/O location has no effect.

Feff =FGX1 x

Asserted Count

Asserted Count + Deasserted Count

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