SC2200 datasheet(173/433 Pages) NSC

173 / 433 page

Revision 3.0

173

www.national.com

Core Logic Module (Continued)

General Purpose Timers

The Core Logic module contains two general purpose idle

timers, General Purpose Timer 1 (F0 Index 88h) and Gen-

eral Purpose Timer 2 (F0 Index 8Ah). These two timers are

similar to the Device Idle Timers in that they count down to

zero unless re-triggered, and generate an SMI when they

reach zero. However, these are 8-bit timers instead of 16

bits, they have a programmable timebase, and the events

which reload these timers are configurable. These timers

are typically used for an indication of system inactivity for

Suspend determination.

General Purpose Timer 1 can be re-triggered by activity to

any of the configured User Defined Devices, Keyboard and

Mouse, Parallel and Serial, Floppy disk, or Hard disk.

General Purpose Timer 2 can be re-triggered by a transi-

tion on the GPIO7 signal (if GPIO7 is properly configured).

When a General Purpose Timer is enabled or when an

event reloads the timer, the timer is loaded with the config-

ured count value. Upon expiration of the timer an SMI is

generated and a status flag is set. Once expired, this

counter must be re-initialized by disabling and enabling it.

The timebase for both General Purpose Timers can be

configured as either 1 second (default) or 1 millisecond.

The registers at F0 Index 89h and 8Bh are the control reg-

isters for the General Purpose Timers.

ACPI Timer Register

The ACPI Timer register (F1BAR0+I/O Offset 1Ch or at

F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The

counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI

generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI

is generated when bit 23 toggles.

Power Management SMI Status Reporting Registers

The Core Logic module updates status registers to reflect

the SMI sources. Power management SMI sources are the

device idle timers, address traps, and general purpose I/O

pins.

Power management events are reported to the GX1 mod-

ule through the active low SMI# signal. When an SMI is ini-

tiated, the SMI# signal is asserted low and is held low until

all SMI sources are cleared. At that time, SMI# is deas-

serted.

All SMI sources report to the Top Level SMI Status register

(F1BAR0+I/O Offset 02h) and the Top Level SMI Status

Mirror register (F1BAR0+I/O Offset 00h). The Top SMI Sta-

tus and Status Mirror registers are the top level of hierarchy

for the SMI Handler in determining the source of an SMI.

These two registers are identical except that reading the

Since all SMI sources report to the Top Level SMI Status

requiring a second level of SMI status reporting. The sec-

ond level of SMI status reporting is set up very much like

the top level. There are two status reporting registers, one

“read only” (mirror) and one “read to clear”. The data

returned by reading either offset is the same, the difference

between the two being that the SMI can not be cleared by

reading the mirror register.

Figure5-11on page174 shows anexample SMItreefor

checking and clearing the source of General Purpose Tim-

ers and the User Defined Trap generated SMI.

SC2200 датащи(PDF) 173 Page - National Semiconductor (TI)

SC2200 датащи(HTML) 173 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL