SC2200 datasheet(134/433 Pages) NSC

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134

Revision 3.0

SuperI/O Module (Continued)

Master Error Detection

The ACB detects illegal Start or Stop Conditions (i.e., a

Start or Stop Condition within the data transfer, or the

acknowledge cycle) and a conflict on the data lines of the

ACCESS.bus. If an illegal condition is detected, ACBST[5]

is set, and master mode is exited (ACBST[1] is cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a

restart operation fails, ACBST[5] is set to indicate the error.

In some cases, both the device and the other device may

identify the failure and leave the bus idle. In this case, the

start sequence may be incomplete and the ACCESS.bus

may remain deadlocked.

To recover from deadlock, use the following sequence:

Clear ACBST[5] and ACBCST[1].

Wait for a timeout period to check that there is no other

active master on the bus (i.e., ACBCST[1] remains

cleared).

Disable, and re-enable the ACB to put it in the non-

addressed slave mode. This completely resets the

functional block.

At this point, some of the slaves may not identify the bus

error. To recover, the ACB becomes the bus master: it

asserts a Start Condition, sends an address byte, then

asserts a Stop Condition which synchronizes all the slaves.

4.7.8

Slave Mode

A slave device waits in idle mode for a master to initiate a

bus transaction. Whenever the ACB is enabled and it is not

acting as a master (i.e., ACBST[1] is cleared), it acts as a

slave device.

OnceaStart Conditiononthe busis detected, thedevice

checks whether the address sent by the current master

matches either:

• The ACBADDR[6:0] value if ACBADDR[7] = 1.

• The general call address if ACBCTL1[5] 1.

This matchis checkedevenwhenACBST[1]is set.Ifabus

conflict (on ABD or ABC) is detected, ACBST[5] is set,

ACBST[1] is cleared and the device continues to search

the received message for a match.

If an address match or a global match is detected:

The device asserts its ABD pin during the acknowl-

edge cycle.

ACBCST[2]and ACBST[2] areset.IfACBST[0]=1

(i.e., slave transmit mode) ACBST[6] is set to indicate

that the buffer is empty.

If ACBCTL1[2] is set, an interrupt is generated if both

ACBCTL1[2] and ACBCTL16 are set.

The software then reads ACBST[0] to identify the

direction requested by the master device. It clears

ACBST[2] so future byte transfers are identified as

data bytes.

Slave Receive and Transmit

Slave receive and transmit are performed after a match is

detected and the data transfer direction is identified. After a

byte transfer, the ACB extends the acknowledge clock until

the software reads or writes ACBSDA. The receive and

transmit sequences are identical to those used in the mas-

ter routine.

Slave Bus Stall

When operating as a slave, the device stalls the

ACCESS.bus by extending the first clock cycle of a trans-

action in the following cases:

• ACBST[6] is set.

• ACBST[2] and ACBCTL1[6] are set.

Slave Error Detection

The ACB detects illegal Start and Stop Conditions on the

ACCESS.bus (i.e., a Start or Stop Condition within the data

transfer or the acknowledge cycle). When this occurs,

ACBST[5] is set and ACBCST[3:2] are cleared, setting the

ACB as an unaddressed slave.

4.7.9

Configuration

ABD and ABC Signals

The ABD and ABC are open-drain signals. The device per-

mits the user to define whether to enable or disable the

internal pull-up of each of these signals.

ACB Clock Frequency

The ACB permits the user to set the clock frequency for the

ACCESS.bus clock. The clock is set by the ACBCTL2[7:1],

which determines the ABC clock period used by the device.

This clock low period may be extended by stall periods initi-

ated by the ACB or by another ACCESS.bus device. In

case of a conflict with another bus master, a shorter clock

high period may be forced by the other bus master until the

conflict is resolved.

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