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Revision 3.0

SuperI/O Module (Continued)

4.7.4

Acknowledge After Every Byte Rule

Accordingtothisrule, themaster generates anacknowl-

edge clock pulse after each byte transfer, and the receiver

sends an acknowledge signal after every byte received.

There are two exceptions to this rule:

• When the master is the receiver, it must indicate to the

transmitter the end of data by not acknowledging (nega-

tive acknowledge) the last byte clocked out of the slave.

This negative acknowledge still includes the acknowl-

edge clock pulse (generated by the master), but the

ABD line is not pulled down.

• When the receiver is full, otherwise occupied, or a

problem has occurred, it sends a negative acknowledge

to indicate that it cannot accept additional data bytes.

4.7.5

Addressing Transfer Formats

Each device on the bus has a unique address. Before any

data is transmitted, the master transmits the address of the

slave being addressed. The slave device should send an

acknowledge signal on the ABD line, once it recognizes its

address.

Theaddress consists of thefirst 7bits after aStart Condi-

tion. The direction of the data transfer (R/W#) depends on

the bit sent after the address, the eighth bit. A low-to-high

transition during a ABC high period indicates the Stop Con-

dition, and ends the transaction of ABD (see Figure 4-17).

When the address is sent, each device in the system com-

pares this address with its own. If there is a match, the

device considers itself addressed and sends an acknowl-

edge signal. Depending on the state of the R/W# bit (1 =

Read, 0 = Write), the device acts either as a transmitter or

a receiver.

The I2C bus protocol allows a general call address to be

sent to all slaves connected to the bus. The first byte sent

specifies the general call address (00h) and the second

byte specifies the meaning of the general call (for example,

write slave address by software only). Those slaves that

require data acknowledge the call, and become slave

receivers; other slaves ignore the call.

4.7.6

Arbitration on the Bus

Multiple master devices on the bus require arbitration

between their conflicting bus access demands. Control of

the bus is initially determined according to address bits and

clock cycle. If the masters are trying to address the same

slave, data comparisons determine the outcome of this

arbitration. In master mode, the device immediately aborts

a transaction if the value sampled on the ABD line differs

from the value driven by the device. (An exception to this

rule is ABD while receiving data. The lines may be driven

low by the slave without causing an abort.)

The ABC signal is monitored for clock synchronization and

to allow the slave to stall the bus. The actual clock period is

set by the master with the longest clock period, or by the

slave stall period. The clock high period is determined by

the master with the shortest clock high period.

When an abort occurs during the address transmission, a

master that identifies the conflict should give up the bus,

switch to slave mode and continue to sample ABD to check

if it is being addressed by the winning master on the bus.

4.7.7

Master Mode

Requesting Bus Mastership

An ACCESS.bus transaction starts with a master device

requesting bus mastership. It asserts a Start Condition, fol-

lowed by the address of the device it wants to access. If

this transaction is successfully completed, the software

may assume that the device has become the bus master.

For the device to become the bus master, the software

should perform the following steps:

Configure ACBCTL1[2] to the desired operation mode.

(Polling or Interrupt) and set the ACBCTL1[0]. This

causes theACB to issueaStart Conditiononthe

ACCESS.bus when the ACCESS.bus becomes free

(ACBCST[1] is cleared, or other conditions that can

delay start). It then stalls the bus by holding ABC low.

If a bus conflict is detected (i.e., another device pulls

down the ABC signal), the ACBST[5] is set.

If there is no bus conflict, ACBST[1] and ACBST[6] are

set.

If the ACBCTL1[2] is set and either ACBST[5] or

ACBST[6] is set, an interrupt is issued.

Figure 4-17. A Complete ACCESS.bus Data Transaction

Start

Condition

Stop

Condition

ABD

ABC

1- 7

1-7

Address R/W ACK

Data

ACK

Data

ACK

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