SC2200 datasheet(133/433 Pages) NSC

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SuperI/O Module (Continued)

Sending the Address Byte

When the device is the active master of the ACCESS.bus

(ACBST[1] is set), it can send the address on the bus.

The address sent should not be the device’s own address,

as defined by ACBADDR[6:0] if ACBADDR[7] is set, nor

should it be the global call address if ACBST[3] is set.

To send the address byte, use the following sequence:

For a receive transaction where the software wants

only one byte of data, it should set ACBCTL1[4]. If only

an address needs to be sent or if the device requires

stall for some other reason, set ACBCTL1[7].

Write the address byte (7-bit target device address)

andthe directionbit to theACBSDAregister. This

causes the ACB to generate a transaction. At the end

of this transaction, the acknowledge bit received is

copied to ACBST[4]. During the transaction, the ABD

and ABC lines are continuously checked for conflict

with other devices. If a conflict is detected, the transac-

tion is aborted, ACBST[5] is set and ACBST[1] is

cleared.

If ACBCTL1[7] is set and the transaction was success-

fully completed (i.e., both ACBST[5] and ACBST[4] are

cleared), ACBST[3] is set. In this case, the ACB stalls

any further ACCESS.bus operations (i.e., holds ABC

low). If ACBCTL1[2] is set, it also sends an interrupt

request to the host.

If the requested direction is transmit and the start

transaction was completed successfully (i.e., neither

ACBST[5] nor ACBST[4] is set, and no other master

has accessed the device), ACBST[6] is set to indicate

that the ACB awaits attention.

If the requested direction is receive, the start transac-

tion was completed successfully and ACBCTL1[7] is

cleared, the ACB starts receiving the first byte auto-

matically.

Check that both ACBST[5] and ACBST[4] are cleared.

If ACBCTL1[2] is set, an interrupt is generated when

ACBST[5] or ACBST[4] is set.

Master Transmit

After becoming the bus master, the device can start trans-

mitting dataonthe ACCESS.bus.

To transmit a byte in an interrupt or polling controlled oper-

ation, the software should:

Check that both ACBST[5] and ACBST[4] are cleared,

andthatACBST[6]isset.IfACBCTL1[7]is set,also

check that ACBST[3] is cleared (and clear it if

required).

Write the data byte to be transmitted to the ACBSDA.

When either ACBST[5] or ACBST[4] is set, an interrupt is

generated. When the slave responds with a negative

acknowledge, ACBST[4] Register is set and ACBST[6]

remains cleared. In this case, if ACBCTL1[2] Register is

set, an interrupt is issued.

Master Receive

After becoming the bus master, the device can start receiv-

ing data on the ACCESS.bus.

To receiveabyteinaninterrupt or pollingoperation, the

software should:

CheckthatACBST[6]isset andthatACBST[5]is

cleared. If ACBCTL1[7] is set, also check that the

ACBST[3] is cleared (and clear it if required).

Set ACBCTL1[4] to 1, if the next byte is the last byte

that should be read. This causes a negative acknowl-

edge to be sent.

Read the data byte from the ACBSDA.

Before receiving the last byte of data, set ACBCTL1[4].

4.7.7.1

Master Stop

To end a transaction, set the ACBCTL1[1] before clearing

the current stall flag (i.e., ACBST[6], ACBST[4], or

ACBST[3]). This causes the ACB to send a Stop Condition

immediately, and to clear ACBCTL1[1]. A Stop Condition

may be issued only when the device is the active bus mas-

ter (i.e., ACBST[1] is set).

Master Bus Stall

The ACB can stall the ACCESS.bus between transfers

while waiting for the host response. The ACCESS.bus is

stalled by holding the AB1C signal low after the acknowl-

edge cycle. Note that this is interpreted as the beginning of

the following bus operation. The user must make sure that

the next operation is prepared before the flag that causes

the bus stall is cleared.

The flags that can cause a bus stall in master mode are:

• Negative acknowledge after sending a byte (ACBST[4] =

1).

• ACBST[6] bit is set.

• ACBCTL1[7] = 1, after a successful start (ACBST[3] =

1).

Repeated Start

A repeated start is performed when the device is already

the bus master (ACBST[1] is set). In this case, the

ACCESS.bus is stalled and the ACB awaits host handling

due to: negative acknowledge (ACBST[4] = 1), empty

buffer (ACBST[6] = 1) and/or a stall after start (ACBST[3]

1).

For a repeated start:

Set \ACBCTL1[0] to 1.

In master receive mode, read the last data item from

ACBSDA.

Follow the address send sequence, as described in

Section "Sending the Address Byte". If the ACB was

awaiting handling due to ACBST[3] = 1, clear it only

after writing the requested address and direction to

ACBSDA.

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