SC2200 datasheet(209/433 Pages) NSC

209 / 433 page

Revision 3.0

209

www.national.com

Core Logic Module (Continued)

ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state.

0: Disable.

1: Enable.

ACPI C3 Support Enable. Allow support of C3 states.

0: Disable.

1: Enable.

Index 64h-6Dh

Reserved

Reset Value: 00h

Index 6Eh-6Fh

ROM Mask Register (R/W)

Reset Value: FFF0h

15:8

Reserved. Must be set to FFh.

7:4

ROM Size. If F0 Index 52h[2] = 1:

0000: 16 MB = FF000000h-FFFFFFFFh

1000: 8 MB = FF800000h-FFFFFFFFh

1100: 4 MB = FFC00000h-FFFFFFFFh

1110: 2 MB = FFE00000h-FFFFFFFFh

1111: 1 MB = FFF00000h-FFFFFFFFh

All other settings for these bits are reserved.

3:0

Reserved. Must be set to 0.

Index 70h-71h

IOCS1# Base Address Register (R/W)

Reset Value: 0000h

15:0

I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1#

(EBGA ball H2 or AL12 / TEPBGA ball D10 or N30 - see PMR[23] in Table 3-2 on page 81).

This register is used in conjunction with F0 Index 72h (IOCS1# Control register).

Index 72h

IOCS1# Control Register (R/W)

Reset Value: 00h

This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).

I/O Chip Select 1 Positive Decode (IOCS1#).

0: Disable.

1: Enable.

Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0

Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.

0: Disable.

1: Enable.

Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0

Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.

0: Disable.

1: Enable.

4:0

IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#.

00000: 1 Byte

01111: 16 Bytes

00001: 2 Bytes

11111: 32 Bytes

00011: 4 Bytes

All other combinations are reserved.

00111: 8 Bytes

Index 73h

Reserved

Reset Value: 00h

Index 74h-75h

IOCS0# Base Address Register (R/W)

Reset Value: 0000h

15:0

I/O Chip Select 0 Base Address. This 16-bit value represents the I/O base address used to enable the assertion of

IOCS0# (EBGA ball J4 / TEPBGA ball A10 - see PMR[23] in Table 3-2 on page 81).

This register is used in conjunction with F0 Index 76h (IOCS0# Control register).

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

SC2200 датащи(PDF) 209 Page - National Semiconductor (TI)

SC2200 датащи(HTML) 209 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL