ATtiny167-ESSZ datasheet(197/282 Pages) ATMEL

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197

7728D–AVR–07/09

ATtiny87/ATtiny167

Figure 17-7. ADC Timing Diagram, Free Running Conversion

17.6

Changing Channel or Reference Selection

The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a tempo-

rary register to which the CPU has random access. This ensures that the channels and

reference selection only takes place at a safe point during the conversion. The channel and

reference selection is continuously updated until a conversion is started. Once the conversion

starts, the channel and reference selection is locked to ensure a sufficient sampling time for

the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion

completes (ADIF in ADCSRA register is set). Note that the conversion starts on the following

rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel

or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

When ADATE or ADEN is cleared.

During conversion, minimum one ADC clock cycle after the trigger event.

After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

Table 17-1.

ADC Conversion Time

Condition

Sample & Hold

(Cycles from Start of Conversion)

Conversion Time (Cycles)

First conversion

13.5 cycles

25 cycles

Normal conversions

1.5 cycles

13 cycles

Auto Triggered conversions

2 cycles

13.5 cycles

Sign and MSB of Result

LSB of Result

DC Clock

DSC

DIF

DCH

DCL

ycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

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