ATtiny167-ESSZ datasheet(193/282 Pages) ATMEL

193 / 282 page

193

7728D–AVR–07/09

ATtiny87/ATtiny167

17.3

Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approx-

imation. The minimum value represents AGND and the maximum value represents the voltage

on AVcc, the voltage refrence on AREF pin or an internal 1.1V / 2.56V voltage reference.

The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in

ADMUX and AREFEN bit in AMISCR. The AVcc supply, the AREF pin or an internal 1.1V /

2.56V voltage reference may be selected as the ADC voltage reference.

The analog input channel and differential gain are selected by writing to the MUX[4..0] bits in

ADMUX register. Any of the 11 ADC input pins ADC[10..0] can be selected as single ended

inputs to the ADC. The positive and negative inputs to the differential gain amplifier are

described in Table 17-5.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input pair by the selected gain factor 8x or 20x, according to the setting

of the MUX[4..0] bits in ADMUX register. This amplified value then becomes the analog input

to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.

The on-chip temperature sensor is selected by writing the code defined in Table 17-5 to the

MUX[4..0] bits in ADMUX register when its dedicated ADC channel is used as an ADC input.

A specific ADC channel (defined in Table 17-5) is used to measure the voltage to the boundar-

ies of an external resistance flowing by a current driving by the Internal Current Source

(ISRC).

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA register. Voltage refer-

ence and input channel selections will not go into effect until ADEN is set. The ADC does not

consume power when ADEN is cleared, so it is recommended to switch off the ADC before

entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX register.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH

is read, neither register is updated and the result from the conversion is lost. When ADCH is

read, ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When

ADC access to the data registers is prohibited between reading of ADCH and ADCL, the inter-

rupt will trigger even if the result is lost.

ATtiny167-ESSZ датащи(PDF) 193 Page - ATMEL Corporation