ATtiny167-ESSZ datasheet(195/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

17.5

Prescaling and Conversion Timing

Figure 17-3. ADC Prescaler

By default, the successive approximation circuitry requires an input clock frequency between

50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed,

the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA

ADEN bit in ADCSRA register. The prescaler keeps running for as long as the ADEN bit is set,

and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA register, the

conversion starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is

switched on (ADEN in ADCSRA register is set) takes 25 ADC clock cycles in order to initialize

the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-

version and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver-

sion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a

new conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This

assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-

ple-and-hold takes place 2 ADC clock cycles after the rising edge on the trigger source signal.

Three additional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conversion

completes, while ADSC remains high. For a summary of conversion times, see Table 17-1.

7-bit ADC Prescaler

Reset

CLK

ADEN

Start

ADPS0

ADPS1

ADPS2

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