AD9549 datasheet(30/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 30 of 78

The min(), max(), floor(), ceil() and round() functions are

defined as follows. The function, min(x1, x2, … xn), chooses the

smallest value in the list of arguments. The function, max(x1,

x2, … xn), chooses the largest value in the list of arguments. The

function, ceil(x), increases x to the next higher integer if x is

NOT an integer, otherwise x is unchanged. The function,

floor(x), reduces x to the next lower integer if x is NOT an

integer, otherwise x is unchanged. The function, round(x),

rounds x to the nearest integer.

To demonstrate the wide programmable range of the loop filter

bandwidth, consider the following design example. The system

clock frequency (fS) is 1GHz, the input reference frequency (fR)

is 19.44MHz, the DDS output frequency (fDDS) is 155.52MHz,

and the required phase margin (φ) is 45°. fR is within the

nominal bandwidth of the phase detector (25MHz), and fDDS/fR,

is an integer (8), so the prescalar is not required. We can

therefore use R=1 and S=8 for the feedforward and feedback

dividers, respectively.

NOTE: If fDDS/fR is a non- integer, then R and S must be chosen

such that S/R= fDDS/fR with S and R both constrained to integer

values. For example, if fR=10MHz and fDDS=155.52MHz, then

the optimal choice for S and R is 1944 and 125, respectively.

The open loop bandwidth range under the defined conditions

spans 9.5Hz to 257.5kHz. The wide dynamic range of the loop

filter coefficients allows for programming of any open loop

bandwidth within this range under these conditions. The

resulting closed loop bandwidth range under the same

conditions is approximately 12Hz to 359kHz.

The resulting loop filter coefficients for the upper loop

bandwidth along with the necessary programming values are

shown below.

α = 4322509.4784981

= 3393 (D41h)

= 2111 (83Fh)

= 0 (0h)

= 22 (16h)

γ = -0.12499215775201

= 0 (0h)

= 4095 (FFFh)

β = -0.10354689386232

= 0 (0h)

The resulting loop filter coefficients for the lower loop

bandwidth along with the necessary programming values are

shown below.

α = 0.005883404361345

= 16 (10h)

= 1542 (606h)

= 7 (7h)

= 0 (00h)

γ = -0.00000461136116

= 7 (7h)

= 19 (13h)

β = -0.000003820176667

= 7 (7h)

Details on exactly how these coefficients are derived can be

obtained by contacting Analog Devices Inc. directly.

CLOSED LOOP PHASE OFFSET

The AD9549 provides for limited control over the phase offset

between the reference input signal and the output signal by

adding a constant phase offset value to the output of the phase

detector. An adder is included at the output of the phase

detector as shown in the figure below to support this. The value

of the constant (PLLOFFSET) is set via the PLL Offset register.

Phase

Detector

Loop

Filter

Phase

Offset

Value

CLK

Feedback

CCI

Filter

Figure 14: Input Phase Offset Adder

PLLOFFSET is a function of the phase detector gain and the

desired amount of timing offset (∆tOFFSET). It is given by:

(

)

Gain

FPFD

PLL

OFFSET

∆

NOTE: FPFD_Gain is described in the Fine Phase Detector

section.

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