AD9549 datasheet(42/78 Pages) AD

42 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 42 of 78

SYSCLK INPUTS

Functional Description

The SysClk pins are where an external timebase is connected to

the AD9549 for generating the internal high frequency system

clock (fS).

The SysClk inputs can be operated in one of three modes: 1)

SysClk PLL Bypassed, 2) SysClk PLL Enabled with input signal

generated externally, or 3) Crystal Resonator with SysClk PLL

Enabled. A functional diagram of the system clock generator is

shown below.

Figure 28: System Clock Generator Block Diagram

The SysClk PLL multiplier path is enabled by a logic 0 (default)

in the PD SysClk PLL location of the I/O Register Map. The

SysClk PLL multiplier can be driven from the SysClk input pins

by one of two means depending on the logic level applied to the

1.8V CMOS CLKMODESEL pin. When CLKMODESEL=0, a

crystal can be connected directly across the SysClk pins. When

CLKMODESEL=1, the maintaining amp is disabled, and an

external frequency source (oscillator, signal generator, etc.) can

be connected directly to the SysClk input pins. Note that

CLKMODESEL=1 does not disable the system clock PLL.

When the SysClk PLL multiplier path is disabled, the AD9549

must be driven by a high frequency signal source (up to 1GHz).

The signal thus applied to the SysClk input pins becomes the

internal DAC sampling clock (fS) after passing through an

internal buffer.

Bipolar Edge Detector

The SysClk PLL Multiplier path offers an optional Bipolar Edge

Detector (BED). This block acts as a frequency doubler by

generating a pulse on each edge of the SysClk input signal. The

SysClk PLL Multiplier locks to the falling edges of this

regenerated signal.

The impetus for doubling the frequency at the input of the

SysClk PLL Multiplier is that an improvement in overall phase

noise performance can sometimes be realized. The main

drawback is that the BED output not a rectangular pulse with a

constant duty cycle even for a perfectly symmetric SysClk input

signal. This results in a sub-harmonic appearing at the same

frequency as the SysClk input signal, and the magnitude of the

sub-harmonic can be quite large. When employing the BED

care must be taken to ensure that the loop bandwidth of the

SysClk PLL Multiplier will adequately suppress the sub-

harmonic.

The benefit offered by the BED depends on the magnitude of

the sub-harmonic, the loop bandwidth of the SysClk PLL

Multiplier, and the overall phase noise requirements of the

specific application. In many applications, the AD9549 clock

output is applied to the input of another PLL, and the sub-

harmonic is often suppressed by the relatively narrow

bandwidth of the downstream PLL.

NOTE: Generally, the benefits of the Bipolar Edge Detector are

realized for SysClk input frequencies of 25MHz and above.

SysClk PLL Multiplier

When the SysClk PLL Multiplier path is employed, the

frequency applied to the SysClk input pins must be limited so as

not to exceed the maximum input frequency of the SysClk PLL

phase detector. A block diagram of the SysClk generator

appears in Figure 29 below.

Figure 29: Block Diagram of the SysClk PLL

The SysClk PLL Multiplier has a 1GHz VCO at its core. A

phase/frequency detector (PFD) and charge pump provide the

steering signal to the VCO in typical PLL fashion. The PFD

operates on the falling edge transitions of the input signal,

which means that the loop locks on the negative edges of the

reference signal. The charge pump gain is controlled via the

I/O Register Map by selecting one of three possible constant

current sources ranging from 125-375µA in 125µA steps. The

center frequency of the VCO is also adjustable via the I/O

feedback path from VCO to PFD consists of a fixed divide-by-2

prescaler followed by a programmable divide-by-N block,

where 2 ≤ N ≤ 33. This limits the overall divider range to any

even integer from 4 to 66, inclusive. The value of N is

AD9549 датащи(PDF) 42 Page - Analog Devices

AD9549 датащи(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL