AD9549 datasheet(23/78 Pages) AD

23 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 23 of 78

PLL CORE (DPLLC)

The Digital Phase Locked Loop Core (DPLLC) includes the

frequency estimation block and the digital phase lock control

block driving the DDS.

The start of the DPLLC signal chain is the reference signal, fR,

which appears on REF A or REF B inputs. The frequency of

this signal can be divided by an integer factor of R via the

feedforward divider. The output of the feedforward divider is

routed to the phase/frequency detector (PFD). Therefore, the

frequency at the input to the PFD is given by

PFD

The PFD outputs a time series of digital words that are routed

to the digital loop filter. The digital filter implementation offers

many advantages: The filter response is determined by numeric

coefficients rather than discrete component values. There is no

aging of components and therefore, no drift of component value

over time. There is no thermal noise in the loop filter, and there

is no control node leakage current (which causes reference feed

through in a traditional analog PLL).

The output of the loop filter is a time series of digital words.

These words are applied to the frequency tuning input of a DDS

to steer the DCO frequency. The DDS provides an analog

output signal via an integrated DAC, effectively mimicking the

operation of an analog VCO.

The DPLLC can be programmed to operate in conjunction with

an internal frequency estimator to help decrease the time

required to achieve lock. When the frequency estimator is

employed, frequency acquisition is accomplished in a two-step

process:

Step 1: An estimate is made of the frequency of fPFD. The phase-

lock control loop is essentially inoperative during the frequency

estimation process. Once a frequency estimate is made, it is

delivered to the DDS so that its output frequency is

approximately equal to fPFD multiplied by S (the modulus of the

feedback divider).

Step 2: The phase-lock control loop becomes active and acts as a

servo to acquire and hold phase lock with the reference signal.

As mentioned in step 1) above, the DPLLC includes a feedback

divider that allows the DCO to operate at an integer multiple

(S) of fPFD. This establishes a nominal DCO frequency (fDDS)

given by:

()

DDS

Figure 9: AD9549 Digital PLL Block Diagram

Feedforward Divider (Divide-by-R)

The feedforward divider is an integer divider allowing

frequency prescaling of the REF Source input signal while

maintaining the desired low jitter performance of the AD9549.

The feedforward divider is a programmable modulus divider

with very low jitter injection. The divider is capable of handling

input frequencies as high as 750 MHz. The divider depth is 16-

bits cascaded with an additional divide-by-two. The divider

therefore is capable of integer division from 1 to 65,535 (index

of 1) or 2 to 131,070 (index of 2). The divider is programmed

via the I/O Register Map to trigger on either the rising (default)

or falling edge of the REF Source input signal.

There is a lower bound on the value of R imposed by the phase-

frequency detector within the DPLLC which has a maximum

operating frequency of fPFD[max] as explained in the Fine Phase

Detector section. The “R Divider /2” bit must be set when

REF_A or REF_B is greater than 400 MHz. The user must also

ensure that R is chosen so that it satisfies the inequality:

R ≥ ceil(fR / fPFD[max])

The upper bound is:

R ≤ floor(fR /8 kHz)

Where the ceil(x) function yields the nearest integer ≥ x. For

example, if fR=155 MHz and fPFD[max] =24.5 MHz, then ceil

(155/24.5) = 7, so R must be > 7.

Feedback Divider (Divide-by-S)

The feedback divider is an integer divider allowing frequency

multiplication of the REF signal that appears at the input of the

phase detector. It is capable of handling frequencies well above

the Nyquist limit of the DDS. The divider depth is 16-bits

cascaded with an additional divide-by-two. The divider is

therefore capable of integer division from 1 to 65,535 (index of

AD9549 датащи(PDF) 23 Page - Analog Devices

AD9549 датащи(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL