AD9549 datasheet(48/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 48 of 78

As an example, consider the system conditions specified below:

fS = 400MHz

fREF_IN = 155.52MHz

R = 8

=0.00005 (i.e., 50ppm)

These conditions yield KMAX=3185, which is the largest K value

that can be programmed without causing the frequency

estimator counter to overflow. With K=KMAX we find that

Tmeas=163.84µs and ε=30.2ppm. KMAX will generally (but not

always) yield the smallest value of ε, but this comes at the cost

of the largest measurement time (Tmeas).

If the measurement time must be reduced, then KHI can be used

instead of KMAX. This yields: KHI=1945, Tmeas=100.05µs, and

ε=39.4ppm.

The measurement time can be further reduced (though

marginally) by using K1 instead of KHI. K1 is found by solving

the ε ≤ ε0 inequality iteratively. To do so, start with K=KHI and

decrement K successively while evaluating the inequality for

each value of K. Stop the process the first time that the

inequality is no longer satisfied and add 1 to the value of K thus

obtained. The result is the value of K1. For the above example,

K1=1912, Tmeas=98.35µs, and ε=39.8ppm.

If a further reduction of the measurement time is necessary,

then K0 can be used. K0 is found in a manner similar to K1.

Start with K=KLO and increment K successively while evaluating

the inequality for each value of K. Stop the process the first

time that the inequality is satisfied. The result is the value of K0.

For the above example, K0=1005, Tmeas=51.70µs and ε=49.0ppm.

STATUS AND WARNINGS

Status Pins

Four pins (S1 – S4) are reserved for providing device status

information to the external environment. These four pins are

individually programmable (via the serial I/O port) as an OR'd

combination of six possible status indications. Each pin has a

dedicated group of control register bits that determine which

internal status flags are used to provide an indication on a

particular pin (as shown in the diagram below).

Internal

Status Flags

RefA LOR

RefA OOL

RefA Invalid

RefB LOR

RefB OOL

RefB Invalid

Phase Lock Detect

Frequency Lock Detect

IRQ

Status Pin Control Register

(1 of 4)

RefAB LOR

Phase Lock

RefAB OOL

IRQ

RefAB Invalid

RefAB

Frequency Lock

Status Pin

(1 of 4)

Ref LOR

Ref OOL

Ref Invalid

Phase Lock

Freq. Lock

IRQ

Figure 35: Status Pin Control

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