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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9549 датащи(PDF) 76 Page - Analog Devices |
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AD9549 датащи(HTML) 76 Page - Analog Devices |
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76 / 78 page  AD9549 Preliminary Technical Data Rev. PrA | Page 76 of 78 0404; FPFD Gain [7:0] FPFD Gain: This register is the fine phase frequency detector linear multiplier (alters charge-pump current). See “Fine Phase Detector” on Page 27. Note that the correct value for this register will be calculated by filter design software provided with the evaluation board. 0405 – 0408; Unused 0409 – 040A; PFD Offset [13:0] DPLL Phase Offset: This register controls the static time offset of the PFD (Phase Frequency Detector) in closed-loop mode. It has no effect when the DPLL is open. 040B; DAC Full-scale Current: [7:0] DAC Full-scale Current: DAC Full-scale Current [7:0]. See “DAC Output” on Page 27. 040C; DAC Full-scale Current [1:0] DAC Full-scale Current: DAC Full-scale Current [9:8]. See Register 040B. 040D – 040E; Unused 040F; Reference Bias Level [1:0] DC Input Level for VDDX @ 3.3 V: This register sets the DC bias level for the reference inputs. The value should be chosen such that VIH is as close as possible to (but not exceeding) 3.3V. 00: VDD3 – 800 mV 01: VDD3 – 400 mV 10: VDD3 – 1.6 V 11: VDD3 – 1.2 V [7:2] Reserved 0410; Unused |
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