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AD9549 датащи(PDF) 41 Page - Analog Devices |
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AD9549 датащи(HTML) 41 Page - Analog Devices |
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41 / 78 page ![]() Preliminary Technical Data AD9549 Rev. PrA | Page 41 of 78 FDBK INPUTS The FDBK pins serve as the input to the feedback path of the digital PLL. Typically, these pins are used to receive the signal generated by the DDS after it has been band-limited by the external reconstruction filter. A diagram of the FDBK input pins is provided here, which includes some of the internal components used to bias the input circuitry. Note that the FDBK input pins are internally biased to a DC level of ~1V. Care should be taken to ensure that any external connections do not disturb the DC bias, as this may significantly degrade performance. To S-Divider and Clock Output Section VSS ~2pF ~1V VSS ~1pF ~1pF FDBK_IN FDBK_INB + Figure 26: Differential FDBK Inputs REFERENCE INPUTS Reference Clock Receiver The Reference Clock receiver is the point at which the user supplies the input clock signal that the Synchronizer will synthesize into an output clock. The clock receiver circuit is able to handle a relatively broad range of input levels as well as frequencies from 8 kHz up to 750 MHz. The following is a diagram of the REFA/B input pins, which includes some of the internal components used to bias the input circuitry. Note that the REF input pins are internally biased by a DC source, Vb. Care should be taken to ensure that any external connections do not disturb the DC bias, as this may significantly degrade performance. To Reference Monitor and Switching Logic VSS ~1pF ~1pF REFA_IN REFA_INB (or REFB_IN) (or REFB_INB) GND 1pF Vb VDD + Figure 27: Reference Inputs NOTE: Support for redundant reference clocks is achieved by using the two Reference Clock receivers (REFA & REFB). In order to accommodate a variety of input signal conditions the value of Vb is programmable via a pair of bits in the I/O Register Map. Table 3 below gives the value of Vb for the bit pattern in Register 040F. Reference Bias Level R040F[1:0] Vb 00 (default) AVDD3-800mV 01 AVDD3-400mV 10 AVDD3-1600mV 11 AVDD3-1200mV Table 3: Setting of Input Bias Voltage (Vb) |
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