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AD9549 датащи(PDF) 43 Page - Analog Devices

номер детали AD9549
подробное описание детали  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9549 датащи(HTML) 43 Page - Analog Devices

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Preliminary Technical Data
AD9549
Rev. PrA | Page 43 of 78
programmed via the I/O Register Map via a 5-bit word that
spans a range of 0 to 31, but the internal logic automatically
adds a bias of 2 to the value entered, extending the range to 33.
Care should be taken when choosing these values so as to not
exceed the maximum input frequency of the Sysclk PLL phase
detector or bipolar edge detector. These values can be found in
the AC Electrical Characteristics section of this datasheet.
External Loop Filter (SysClk PLL)
The loop bandwidth of the SysClk Multiplier PLL can be
adjusted by means of three external components as shown in
the diagram below. The nominal gain of the VCO is
800MHz/V. The recommended component values are shown in
Table 4 below. They establish a loop bandwidth of
approximately 1.6MHz with the charge pump current set to
250µa. The default case is N=40, and assumes a 25MHz SysClk
input frequency and generates an internal DAC sampling
frequency (fS) of 1GHz.
Figure 30: External Loop Filter for SysClk PLL
Sysclk
Multiplier
R1
Series
C1
Shunt
C2
< 8
390Ω
1 nF
82 pF
10
470Ω
820pF
56 pF
20
1kΩ
390pF
27 pF
40 (default)
2.2kΩ
180 pF
10 pF
60
2.7kΩ
120 pF
5 pF
Table 4: Recommended Loop Filter Values for a nominal 1.5MHz
Sysclk PLL loop Bandwidth
Detail of SysClk Differential Inputs
A diagram of the SysClk input pins is provided here. Included
are details of the internal components used to bias the input
circuitry. These components have a direct effect on the static
levels at the SysClk input pins. This information is intended to
aid in determining how best to interface to the device for a
given application.
Note that the SysClk PLL Bypassed and SysClk PLL Enabled
input paths are internally biased to a DC level of ~1V. Care
should be taken to ensure that any external connections do not
disturb the DC bias, as this may significantly degrade
performance. Generally, it is recommended that the SysClk
inputs be AC coupled to the signal source (except when using a
crystal resonator).



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