AD9549 datasheet(68/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 68 of 78

0023; PFD Divider

[3:0] Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes to run the

DPLL Phase detector fast while Sysclk is run relatively slowly. The ratio is equal to PFD Divider * 4. For a 1 GHz system clock,

the ADC runs at 1 GHz / 20 = 50 MHz, and the DPLL phase detector runs at half this speed , which in this case is 25 MHz).

Digital PLL Control and Dividers

0100; PLL Control

[0] Close Loop: Setting this bit closes the loop. If Bit 4 of this register is cleared, then the frequency estimator will be used. If this

bit is cleared and the loop is opened, the user should reset the CCI and LF bits of Register 0012 prior to closing the loop again.

[1] Loop Polarity: This bit reverses the polarity of the loop response.

[2] Unused

[3] Enable Frequency Slew Limiter: This bit enables the frequency slew limiter that controls how fast the tuning word can

change, and is useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. These values are

set in Registers 0127-012C. See “Frequency Slew Limiter” on Page 46.

[4] Disable Frequency Estimator. The Frequency Estimator is normally not used, but is useful when the input frequency is

unknown, or needs to be qualified. This estimate appears in Registers 115-11A. The Frequency Estimator is not needed when

FTW0 (Register 01A6-01AB) is programmed. See “Frequency Estimator“ on Page 47.

[5] Single Tone Mode: Setting this bit allows the 9549 to output a tone open loop using FTW0 as DDS tuning word. This bit

must be cleared when Bit 0 (Close Loop) is set. This is very useful in debugging when the signal coming into the AD9549 is

questionable or nonexistent.

[7:6] Reserved

0101 – 0102; R Divider (DPLL Feedforward Divider)

[15:0] Feedforward Divider (also called the Reference divider) of the DPLL. Divide Ratio: 1 – 65536. See “Feedforward Divider

(Divide-by-R)” on Page 23. If the desired feedfeedforward ratio is greater than 65536, or if the reference input signal on REF_A

or REF_B is greater than 400 MHz, then Bit 0, R103 must be set.

0103; R Divider (continued)

[0] Divide by 2: Setting this bit enables an additional /2 pre-scalar, effectively doubling the range of the Feedforward Divider. If

the desired feedfeedforward ratio is greater than 65536, or if the reference input signal on REF_A or REF_B is greater than 400

MHz, then this bit must be set.

[6:1] Unused

[7] Falling Edge Triggered: Setting this bit inverts the reference clock before R divider.

0104 – 0105; S Divider (DPLL Feedback Divider)

[15:0] Feedback Divider: Divide Ratio: 1 – 65536. If the desired feedback ratio is greater than 65536, or if the feedback signal on

FDBK_IN is greater than 400 MHz, then Bit 0, R106 must be set.

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