AD9549 datasheet(38/78 Pages) AD

38 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 38 of 78

that the device is programmed to revert automatically to a valid

reference when it recovers. When a reference returns to normal

operation, the LOR and OOL conditions will no longer be true.

However, the state machine is not immediately notified of the

clearing of the LOR and OOL condition. Instead, once both the

LOR and OOL conditions are cleared, the recovery timer for

that particular reference is started. Expiration of the recovery

timer is an indication to the state machine that the reference is

now available for selection. However, even though the reference

is now flagged as "valid", actual transition to the recovered

reference depends on the programmed settings of the various

holdover control bits.

The recovery timers are controlled via the I/O Register Map.

Although there are two independent recovery timers, the

programmed information is shared among both. The desired

time interval is controlled via a 5-bit word (T) such that

0 ≤ T ≤ 31 (default is T=0). The duration of the recovery timers

is given by:

(

2 1

−

RECOVER

Where T0 is the sample rate of the digital loop filter, which has a

period of:

0 =

(see the Digital Loop Filter section)

A single bit, Disable Recovery Timer, causes the state machine

to ignore the status of the recovery timers. Instead, the state

machine relies on the user to validate the recovery of the faulty

reference and then to set the Validate RefA (or RefB) bit

manually in the I/O Register Map. That is, the state machine

treats the setting of the "Validate" bits as though the associated

timer had expired.

Holdover Operation

When the holdover condition is asserted, the DDS output

frequency is no longer controlled by the phase lock feedback

loop. Instead, a static frequency tuning word (FTW) is applied

to the DDS to hold it at a specified frequency. The source of the

static FTW depends on the status of the appropriate control

monitors and accumulates up to 65000 FTW values as they are

generated, and upon entering holdover, the holdover state

machine can use the averaged tuning word, or the last valid

tuning word.

Holdover mode is exited in a similar manner that it is entered. If

manual holdover control is used, then when the holdover pin is

de-asserted, the phase detector starts comparing the holdover

signal with the reference input signal, and will start to adjust the

phase/frequency using the holdover signal as its starting point.

The behavior of the holdover state machine when it is in

automatically exiting holdover mode is very similar. The

primary difference is that reference monitor is continuously

monitoring both reference inputs and as soon as one becomes

valid, it automatically switches to that input.

The output frequency in Holdover mode depends on the

frequency of the SysClk input source and the value of the

frequency tuning word applied to the DDS. Therefore, the

stability of the output signal is completely dependent on the

stability of the SysClk source (and the SysClk PLL Multiplier, if

enabled).

Note: It is very important to power down an unused reference

input to avoid chattering on that input. Also, the reference

validation timer must be set to at least one full cycle of the

signal coming out of the reference divider.

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