AD9549 datasheet(24/78 Pages) AD

24 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 24 of 78

1) or 2 to 131,070 (index of 2). The divider is programmed via

the I/O Register Map to trigger on either the rising (default) or

falling edge of the feedback signal.

The feedback divider must be programmed within certain

boundaries. The “S Divider /2” bit must be set when FDBK_IN

is greater than 400 MHz. The upper boundary on the feedback

divider is the lesser of the maximum programmable value of S

and the maximum practical output frequency of the DDS (~

40%fS). Two formulae are given: Smax1 for a feedback divider

index of 1 and Smax2 for an index of 2:

(

)

65535

min

max

[

]

131070

min

max

Where R is the modulus of the feedforward divider, fS is the

DAC sample rate, and fR is the input reference frequency.

The DCO has a minimum frequency (see DAC output

Characteristics section of AC specification table). This imposes

a lower bound, Smin, on the feedback divider value, as well.

(

)

(

max

min

DCO

NOTE: Reduced DCO frequencies result in worse jitter

performance (a consequence of the reduced slew rate of the

sinusoid generated by the DDS).

Forward and Reverse FEC Clock Scaling

The Feedforward (Divide-by-R) and Feedback Divider (Divide-

by-S) enable FEC clock scaling. For instance, to multiply the

incoming signal by 255/237, set the S- divider to 255, and the

R-divider to 237. One should be careful to abide by the

limitations on the R- and S-Dividers, and make sure the Phase

Detector input frequency is within specified limits.

Phase Detector

The phase detector is composed of two detectors: a coarse

phase detector and a fine phase detector. The two detectors

operate in parallel. Both detectors measure the duration (∆t) of

the pulses generated by a conventional 3-state phase/frequency

detector.

Together, the fine and coarse phase detectors produce a digital

word that is a time-to-digital conversion of the separation

between the edge transitions of the pre-scaled reference signal

and the feedback signal.

If the fine phase detector is able to produce a valid result, then

this result alone serves as the phase error measurement. If the

fine phase detector is either in an overflow or underflow

condition, the phase error measurement uses the coarse phase

detector instead.

Digital Loop Filter

The digital loop filter integrates and low-pass filters the digital

phase error values delivered by the phase detector. The loop

filter response mimics that of a 2nd order, R-C network used to

filter the output of a typical phase detector and charge pump

combination as shown in the diagram below.

Phase/

Frequency

Detector

Charge

Pump

Loop Filter

VCO

CLK

Figure 10: Typical Analog PLL Block Diagram

The building blocks implemented on the AD9549, however, are

digital. A time-to-digital converter that produces digital values

proportional to the edge timing error between the CLK and

feedback signals replaces the phase-frequency detector and

charge pump. A digital filter that processes the edge timing

error samples from the time-to-digital converter replaces the

loop filter. A DDS replaces the VCO, which produces a

frequency that is linearly related to the digital value provided by

the loop filter. This is shown in Figure 11 on Page 26 with some

additional detail.

The samples provided by the time-to-digital converter are

delivered to the loop filter at a sample rate equal to the CLK

frequency (i.e., fR/R). The loop filter is intended to oversample

the time-to-digital converter output at a rate determined by the

"P"-divider. The value of P is programmable via the I/O

PIO is related to P by the equation:

P = 2PIO

(where 5 ≤ PIO ≤ 16)

Hence, the "P"-divider can provide divide ratios between 32 and

65536 in power-of-2 steps. With a DAC sample rate of 1GHz

the loop filter sample rate can range from as low as 15.26kHz to

a maximum of 31.25MHz. Coupled to the loop filter is a

cascaded comb-integrator (CCI) filter that provides a sample

rate translation between the loop filter sample rate (fS/P) and

the DDS sample rate, fS.

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