AD9549 datasheet(71/78 Pages) AD

71 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 71 of 78

01C1; Override

[0] Holdover On/Off: This bit controls the status of holdover when Bit 1 of this register is set.

[1] Enable Holdover Override: Setting this bit disables automatic holdover, and allows user to enter/exit holdover manually via

Bit 0 (see above). Setting this bit overrides the HOLDOVER pin.

[2] Ref_AB: This bit selects the input when Bit 3 of this register is set. 0 equals REF_A.

[3] Enable Ref Input Override: Setting this bit disables automatic reference switchover, and allows user to switch references

manually via Bit 2 of this register. Setting this bit overrides the REFSELECT pin.

[4] Enable Line-Card Mode: Enables line-card mode of reference switch MUX, which eliminates the possibility of a runt pulse

during switchover. See “Use of Line Card Mode to Eliminate Runt Pulses” on Page 35.

01C2; Averaging Window

[3:0] FTW Windowed Average Size: This register sets the number of FTWs (frequency tuning words) that are used for

calculating the average FTW. Bit 4 in Register 01C0 enables this feature.

The number of averages equals 2(FTW Windowed Average Size [3:0]). These samples are taken at the rate of (fs / 2^PIO).

01C3; Reference Validation

[4:0] Recovery Timer: The value in this register sets the time required to validate a reference after a LOR or OOL event before

the reference can be used as the DPLL reference. This circuit uses the digital loop filter clock (see Register 0107).

Validation time = Loop filter clock period * 2(Recovery Timer[4:0] +1) -1. Assuming power-on defaults, the recovery time varies from

32 ns (00000) to 137 sec (11111). If longer validation times are required, the user can make the P divider larger.

[6:5] Unused

[7] Disable Recovery Timer: Setting these bits disables the recovery timer and requires that references be manually validated.

(see Register 01C4)

01C4; Reference Validation (continued);

[0] Validate RefB: Mark RefB as valid either prior to the recovery timer or instead of the timer, and is enabled by setting Bit 7 in

[1] Validate RefA: Mark RefA as valid either prior to the recovery timer or instead of the timer, and is enabled by setting Bit 7 in

Doubler and Output Drivers

0200; HSTL Driver

[2:0] HSTL Output Doubler: 01: Doubler disabled. 00: Doubler enabled.

[3:2] Unused

[4] OPOL: Output polarity: Setting this bit inverts the HSTL driver output polarity.

0201; CMOS Driver

[0] User MUX control: This bit allows the user to select whether the CMOS driver output is divided by the S Divider.

0: S divider input sent to CMOS driver. 1: S divider output sent to CMOS driver.

See Figure 8: Detailed Block Diagram on Page 22.

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