AD9549 datasheet(26/78 Pages) AD

26 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 26 of 78

Direct Digital Synthesizer

One of the primary building blocks of the digital PLL is a direct

digital synthesizer (DDS). The DDS behaves like a sinusoidal

signal generator. The frequency of the sinusoid generated by

the DDS is determined by a frequency tuning word (FTW),

which is a digital (i.e., numeric) value. Unlike an analog

sinusoidal generator, a DDS uses digital building blocks and

operates as a sampled system. Thus, it requires a sampling

clock (fS) that serves as the DDS's fundamental timing source.

The accumulator behaves as a modulo-248 counter with a

programmable step size (FTW). A block diagram of the DDS is

shown below.

Frequency

Tuning Word

(FTW)

Angle to

Amplitude

Conversion

Phase

Offset

I-Set

DAC-

DAC+

DAC

(14-bit)

48-bit Accumulator

Figure 11: DDS Block Diagram

The input to the DDS is a 48-bit FTW that provides the

accumulator with a seed value. On each cycle of fS, the

accumulator adds the value of the FTW to the running total of

its output. For example, given an FTW=5, the accumulator

would count by 5's, incrementing on each fS cycle. Over time,

the accumulator will reach the upper end of its capacity (248 in

this case). At which point it rolls over, retaining the excess. The

average rate at which the accumulator rolls over establishes the

frequency of the output sinusoid. The average rollover rate of

the accumulator is given by the formula below, and establishes

the output frequency (fDDS) of the DDS.

( )

FTW

DDS

Solving this equation for FTW yields:

























DDS

round

FTW

For example, given that fS=1GHz and fDDS=19.44MHz, then

FTW=5,471,873,547,255 (04FA05143BF7h).

The relative phase of the sinusoid can be controlled

numerically, as well. This is accomplished using the phase offset

input to the DDS (a programmable 16-bit value (∆phase); see

the I/O Register Map). The resulting phase offset, ∆φ (radians),

is given by:

( )

phase

∆

The DDS can be operated in either open loop or closed loop

mode, via the Close Loop bit in the DPLL Register.

There are two open loop modes: Single Tone and Holdover. In

Single Tone Mode, the DDS behaves like a frequency

synthesizer, and uses the value stored in the FTW0 register to

determine its output frequency. Alternatively, the FTW and

∆phase values can be determined by the device itself using the

frequency estimator. Because Single Tone mode ignores the

reference inputs, it is very useful for generating test signals to

aid in debugging. Single Tone mode must be activated manually

via register programming.

In Holdover mode, the AD9549 uses past tuning words when

the loop was closed to determine its output frequency.

Therefore, the loop must have been successfully closed in order

for Holdover Mode to work. Switching in and out of Holdover

Mode can be either automatic or manual, depending on register

settings.

Typically, the AD9549 operates in closed loop mode. In closed

loop mode, the FTW values come from the output of the digital

loop filter and vary with time. The DDS frequency is steered in

a manner similar to a conventional VCO-based PLL.

NOTE: In "closed loop" mode, the DDS phase offset capability

is inoperative.

AD9549 датащи(PDF) 26 Page - Analog Devices

AD9549 датащи(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL