AD9549 datasheet(27/78 Pages) AD

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Preliminary Technical Data

AD9549

Rev. PrA | Page 27 of 78

DAC Output

The output of the digital core of the DDS is a time series of

numbers representing a sinusoidal waveform. This series is

translated to an analog signal by means of a digital-to-analog

converter (DAC).

The DAC outputs its signal to two pins driven by a balanced

current source architecture (see DAC output diagram below).

The peak output current derives from the combination of two

factors. The first is a reference current (IDAC_REF) established at

the DAC_RSET pin and the second is a scale factor

programmed into the I/O Register map.

AVDD3

Current

Switch

Array

Current

Switch

Array

IFS

Switch

Control

IFS/2

IOUT

IOUTB

AVSS

CODE

IFS/2 + ICODE

IFS/2 - ICODE

Figure 12: DAC Output Pins

The value of IDAC_REF is set by connecting a resistor (RDAC_REF)

between the DAC_RSET pin and ground. The DAC_RSET pin

is internally connected to a virtual voltage reference of 1.2v

nominal, so the reference current can be calculated by:

REF

DAC

REF

DAC

NOTE: The recommended value of IDAC_REF is 120µA, which

leads to a recommended value of RDAC_REF of 10kΩ.

The scale factor consists of a 10-bit binary number (FSC)

programmed into the DAC FS Current register in the I/O

then given by:

(

)

1024

192

FSC

REF

DAC

⋅

Using the recommended value of RDAC_REF the full-scale DAC

output current can be set with 10-bit granularity over a range of

approximately 8.6mA to 31.7mA.

PHASE DETECTOR

Coarse Phase Detector

The coarse phase detector uses the DAC sample rate (fS) to

determine the edge timing deviation between the REF signal

and the feedback signal generated by the DDS. Hence, fS sets

the timing resolution of the coarse phase detector. At the

recommended rate of fS=1GHz, the coarse phase detector spans

a range of over 131µs (sufficient to accommodate REF signal

frequencies as low as 8 kHz).

The phase gain of the coarse phase detector is controlled via the

I/O Registers by means of two numeric entries. The first is a 3-

bit power-of-2 scale factor, PDS. The second is a 6-bit linear

scale factor, PDG.

( )()

PDG

Gain

Phase

PDS

CPD

Fine Phase Detector

The fine phase detector operates on a divided down version of fS

as its sampling time base. The sample rate of the fine phase

detector is set using a 4-bit word (PFD_Div) in the I/O Register

Map and is given by:

()

Div

PFD

Rate

Sample

Detector

Phase

Fine

The default value of PFD_Div is 5, so for fS=1GHz, the default

sample rate of the fine phase detector is 50MHz. The upper

bound on the maximum allowable input frequency to the phase

detector (fPFD[max]) is 49% of the sample rate, or:

()

Div

PFD

[max] =

Therefore, fPFD[max] is 25MHz in the example above.

The fine phase detector uses a proprietary technique to

determine the phase deviation between the REF signal and

feedback signal.

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