AD9549 datasheet(36/78 Pages) AD

36 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 36 of 78

REFA In

REFB In

REF In

Line Card

Mode

Disabled

REF In

From Reference

Selection Logic

Select REFA

Select REFB

Enabled

REF selection stalled until

next rising edge of REFB

Figure 21: Reference Switchover Timing

HOLDOVER

Holdover Control

Holdover functionality provides the user with a means of

maintaining the output clock signal even in the absence of a

reference signal at the REF A or B input. In holdover mode, the

output clock is generated from the SysClk input (via the DDS)

by directly applying a frequency tuning word to the DDS.

Transfer from normal operation to holdover mode may be

accomplished either manually or automatically by appropriately

programming the "Automatic Holdover" bit (0=Manual,

1=Auto). The actual transfer to holdover operation, however,

depends on the state of the HOLDOVER pin and the state of

control register bits "Enable Holdover Override" and "Holdover

On/Off ".

Manual holdover is established when the “Automatic Holdover”

bit is a logic 0 (default). In manual mode, holdover is

determined by the state of the HOLDOVER pin (0=Normal,

1=Holdover). The HOLDOVER pin is configured as a high

impedance (>100kΩ) input pin in order to accommodate

manual holdover operation.

Automatic holdover is invoked when the “AutoHold" bit is a

logic 1. In automatic mode, the HOLDOVER pin is configured

as a low impedance output with its logic state indicating the

holdover state as determined by the internal state machine

(0=Normal, 1=Holdover).

In automatic holdover operation the user may override the

internal state machine by programming the "Override HldPin"

bit to a logic 1 and the "Hldovr" bit to the desired state

(0=Normal, 1=Holdover). However, the HOLDOVER pin does

not indicate the "forced" holdover state in the override

condition, but continues to indicate the holdover state as chosen

by the internal state machine (even though the state machine

choice is overridden). This allows the user to force a holdover

state by means of the programming registers while monitoring

the response of the state machine via the HOLDOVER pin.

A functional diagram of the reference switchover and holdover

logic is shown in Figure 19 on Page 35.

NOTE: The default state for the reference switchover bits is

AutoHold=0, Override HldPin=0, and Hldovr=0.

Holdover & Reference Switchover State Machine

The interplay between the input reference signals and holdover

is most readily demonstrated by means of a state diagram. In

Figure 22, the various control signals and the four states are

shown.

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