AD9549 datasheet(22/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 22 of 78

THEORY OF OPERATION

Figure 8: Detailed Block Diagram

OVERVIEW

The AD9549 provides a clocking output which is directly

related in phase and frequency to the selected (active) reference

(REF_A or REF_B), but having a phase noise spectrum

primarily governed by the system clock. A wide band of

reference frequencies is supported. Jitter existent on the active

reference is greatly reduced by a programmable digital filter in

the Digital Phase Locked Loop (PLL), which is the core of this

product. The AD9549 supports both manual and automatic

holdover. While in holdover, the AD9549 will continue to

provide an output as long as the system clock is maintained.

The frequency of the output during holdover is an average of

the steady state output frequency prior to holdover. Also offered

are manual and automatic switchover modes for changing

between the two references should one become suspect or lost.

A digitally controlled oscillator (DCO) is implemented using a

Direct Digital Synthesizer (DDS) with an integrated output

DAC, clocked by the system clock. A bypassable PLL based

frequency multiplier is present enabling use of an inexpensive,

low frequency source for the system clock. For best jitter

performance, the system clock PLL should be bypassed, and a

low-noise high-frequency system clock should be provided

directly. Sampling theory sets an upper bound for the DDS

output frequency at 50% of fS (where fS is the DAC sample rate),

but a practical limitation of 40% of fS is generally recommended

to allow for the selectivity of the required off-chip

reconstruction filter. The output signal from the reconstruction

filter is fed back to the AD9549, both to complete the PLL, and

to be processed through the output circuitry. The output

circuitry includes HSTL and CMOS output buffers, as well as a

frequency doubler for systems, which need to provide

frequencies above the Nyquist level of the DDS.

The individual functional blocks are described in the following

sections.

DDS/DAC

FREQ

TUNING

WORD

HOLDOVER

CONTROL

LOGIC

DIGITAL

INTERFACE

PFD

÷ S

÷ R

HSTL

CLK_OUT

CMOS

CLK_OUT

INPUT

REF

MONITOR

REF_CNTRL

LOCK DETECT

S1-S4

REF_A

REF_B

REF_SELECT

SYS_CLK

Freq

Est.

Digital PLL Core

SYSCLK PORT

EXTERNAL

ANALOG

LOW-PASS

FILTER

SLEW

LIMIT

PROG.

DIGITAL

LOOP

FILTER

LOW NOISE

CLOCK

MULTIPLIER

AMP

FDBK

IRQ & Status

Logic

OOL&LOR

HOLDOVER

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