AD9549 datasheet(67/78 Pages) AD

67 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 67 of 78

0012; Reset; Auto Clear; To reset the entire chip, the user may also use the (non-self clearing) Soft Reset bit in Register 0000.

Except for IRQ reset, the user normally would not need to use these.

[0] DDS (Direct Digital Synthesis) Reset

[1] CCI (Cascaded Comb Integrator) Reset

[2] LF (Loop Filter) Reset

[3] CPFD (Coarse Phase Frequency Detector) Reset

[4] FPFD (Fine Phase Frequency Detector) Reset

[5] IRQ Reset: Clear IRQ signal and IRQ status monitor

[6] Unused

[7] History Reset: Setting this bit clears the FTW monitor and pipeline.

0013; Reset (continued); NOT Auto Clear.

[0] R Divider Reset: Synchronous (to R divider prescaler output) reset for integer divider

[1] S Divider Reset: Synchronous (to S divider prescaler output) reset for integer divider

[2] R Div2 Reset: Asynchronous reset for R prescaler

[3] S Div2 Reset: Asynchronous reset for S prescalar

[7] PD Fund DDS: Setting this bit powers down the DDS fundamental output, but not the spurs. It is used during tuning of the

Spur Killer circuit.

System Clock

0020; N Divider

[4:0] N Divider: These bits set the Feedback divider for System Clock PLL. There is a fixed /2 preceding this block, as well as a

an offset of 2 added to this value. Therefore, setting this register to 00000 translates to an overall feedback divider ratio of 4. See

Figure 29: Block Diagram of the SysClk PLL on Page 42.

0021; Reserved

0022; PLL Parameters

[1:0] Charge Pump Current: 00: 250 uA , 01: 375 uA, 10: Off, 11: 125 uA

[2] VCO Range: Select low range or high range VCO. 0= low range (700 to 800 MHz). 1= high range (850 to 1000 MHz). For

System clock settings in between 800-850 MHz, use the VCO Auto Range (Bit 7) to set the correct VCO range automatically.

[3] 2x Reference: Enables a frequency doubler prior to the Sysclk PLL and can be useful in reducing jitter induced by the Sysclk

PLL. See Figure 28: System Clock Generator Block Diagram, Page 42.

[4:6] Reserved

[7] VCO Auto Range: Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.

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