AD9549 datasheet(6/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 6 of 78

SYSTEM CLOCK INPUT

SYSCLK PLL BYPASSED

Input Capacitance (DC)

1.5

single-ended, each pin

Input Impedance (DC)

KΩ

differential

Common Mode Input Voltage3

differential operation

Differential Input Voltage Swing3

differential operation

Input Voltage High (VIH)

single-ended operation

Input Voltage Low (VIL)

single-ended operation

Input Current

single-ended operation

SYSCLK PLL ENABLED

Input Capacitance (DC)

single-ended, each pin

Input Impedance (DC)

KΩ

differential

Common Mode Input Voltage3

differential operation

Differential Input Voltage Swing3

differential operation

Input Voltage High (VIH)

single-ended operation

Input Voltage Low (VIL)

single-ended operation

Input Current

single-ended operation

CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED

Motional Resistance

kΩ

CLOCK OUTPUT DRIVERS

HSTL OUTPUT DRIVER

Differential Output Voltage Swing4

TBD

700

Both pins AC-coupled using 0.01uF,

then 50

Ω to GND,

Common Mode Output Voltage4

TBD

0.9

Continuous Output Current

7.2

CMOS OUTPUT DRIVER

Output Voltage High (VOH)

Output Voltage Low (VOL)

0.4

Output High Current (IOH)

µA

Output Low Current (IOL)

µA

TOTAL POWER DISSIPATION

All Blocks Running

TBD

Power-Down Mode

TBD

Using either the Power Down

Default with SysClk PLL Enabled

TBD

After reset or power up with fS=1GHz,

S4=0, S1-S3=1, fSYSCLK=25MHz

Default with SysClk PLL Disabled

TBD

After reset or power up with fS=1GHz,

S4-S4=1, & Sysclk PLL powered down.

- with Digital Power Down

TBD

- with REFA or REFB Power Down

TBD

One reference still powered up.

- with HSTL Clock Driver Power Down

TBD

- with CMOS Clock Driver Power Down

TBD

- with HSTL 2x Freq. Multiplier Power

Down

TBD

1 Must be

≤ 0V relative to AVDD3 (pin 14) and ≥ 0V relative to AVSS (pins 33, 43).

2 Must be

≤ 0V relative to AVDD (pin 42) and ≥ 0V relative to AVSS (pins 33, 43).

3 Relative to AVSS (pins 33, 43).

4 Must be

≤ 0V relative to AVDD (pin 36) and ≥ 0V relative to AVSS (pins 33, 43).

5 See “Power Management” Section for details about power profiles.

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