DA16200 datasheet(115/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

115 of 153

Table 164: HIF_BLK_LG (0x5003_0024)

Bit

Mode

Symbol

Description

Reset

31:28

Reserved

27:16

R/W

HIF_BLK_LG

Block Length Register

This register specifies the length (unit: byte) of each block for

read/write data transfer

8'h0

15:6

Reserved

5:4

R/W

HDOE_DLY

Output Enable Delay Control for Host Data signals

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

3:2

R/W

HDO_DLY

Output Delay Control for Host Data signals

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

1:0

R/W

HDI_DLY

Input Delay Control for Host Data signals

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

Table 165: HIF_BLK_CNT (0x5003_0028)

Bit

Mode

Symbol

Description

Reset

31:24

Reserved

23:0

R/W

HIF_BLK_CNT

Block Count Register

24'h0

Table 166: HIF_RSP_TMO_CNT (0x5003_0030)

Bit

Mode

Symbol

Description

Reset

31:8

Reserved

7:0

R/W

RSP_TMO_CNT

This register specifies the number of host clock cycles for the

response time-out interrupt. If the host cannot receive the

response, it does not return to the host before the specified

clock cycles

8'h40

Table 167: HIF_RD_TMO_CNT (0x5003_0034)

Bit

Mode

Symbol

Description

Reset

31:0

R/W

RD_TMO_CNT

Read Data Time-Out Count Register

This register specifies the number of host clock

cycles for the read data time-out interrupt if the read

data does not return to the host before the specified

clock cycles

8'h0040_0000

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