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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DA16200 датащи(PDF) 45 Page - Renesas Technology Corp |
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DA16200 датащи(HTML) 45 Page - Renesas Technology Corp |
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45 / 154 page  DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 45 of 153 © 2023 Renesas Electronics Figure 19 shows the DMA2 block diagram. DMA2 M0 M1 S AHB BusMatrix Configuration Figure 19: DMA2 Block Diagram 7.8 Simple Memory Protection DA16200 provides simple protection for internal SRAM, ROM, and Retention Memory. The memory controllers are AMBA AHB slaves and simple protection operates between the main AHB bus and the AHB slave port of the memory controllers. The features of memory protection in DA16200 are summarized as follows: ■ Memory protection provides the function to set the security area of each memory that should be protected ■ The setting unit to set the security area for each memory is different: □ SRAM: 1 kB/unit □ MROM: 16 bytes/unit □ Retention Memory: 4 bytes/unit ■ Provides the access protection for the security zone for each AHB master ■ Provides the write protection function for each AHB master ■ Provides the read protection function for each AHB master ■ Latency is 0 cycle The index numbers to distinguish AHB masters are: ● 0x0: Cortex M4 – DCode bus ● 0x1: Cortex M4 – ICode bus ● 0x2: Cortex M4 – System bus ● 0x3: MAC DMA ● 0x4: DMA1 ● 0x5: SD/eMMC (SD Host) ● 0x6: Serial Slave Interface (SPI, I2C, SDIO) ● 0x7: DMA2_M0 (read port) |
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