DA16200 datasheet(113/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

113 of 153

Table 162: HIF_CMD_IDXQ (0x5003_001C)

Bit

Mode

Symbol

Description

Reset

31:16

Reserved

QBUSY_ST

Busy status of the current command queue

0: completed

1: ongoing

1'b0

CMD_TCTLQ

Command Trigger Control Queue

0: Start a new command immediately when the command

trigger (CMDQ_TRIG) bit was set

1: Only start a new command when the command trigger

(CMDQ_TRIG) bit was set and the previous response result

has been read

1'b0

13:12

RSP_TYPEQ

Response Type Control Queue

0x: No Response

10: Short Response (Total: 48 bits)

11: Long Response (Total: 136 bits)

2'b00

STB_CTL

Command Start Bit and Transmission Bit Control Queue

0: The start bit and transmission bit of the SD/eMMC

command is automatically generated by H/W circuit

1: The start bit and transmission bit of the SD/eMMC

command refers to the STR_BIT and TRM_BIT of this

control register

1'b0

10:8

DATA_TYPEQ

Data Type Control Queue

0xx: Command only (without data transfer)

100: Command with single read data

101: Command with multiple read data

110: Command with single write data

111: Command with multiple write data

3'b000

STR_NITQ

This register specifies the value of the start bit of SD/eMMC

command if STB_CTL bit is set to high. Otherwise, it is not

used

1'b0

TRM_BITQ

This register specifies the value of the transmission bit of

SD/eMMC command if STB_CTL bit is set to high.

Otherwise, it is not used

1'b1

5:0

HIF_CMD_IDXQ

This register specifies the value of the SD/eMMC command

index

6'h0

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