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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

46 of 153

● 0x8: DMA2_M1 (write port)

● 0x9: DMA of Crypto Engine

● 0xA: QSPI master – flash controller with XIP

● 0xB: Hardware Security Unit for Temporal Key Integrity Protocol (HSU for TKIP)

● 0xC: SPI master for another external SPI slaves

For more information to use this function, see Ref. [2].

7.9

Bus Protection of Serial Slave Interfaces

DA16200 supports a variety of serial slave interfaces, including SPI, I2C, and SDIO slaves.

When DA16200 interfaces with an external host, it is necessary to provide the access to the

authorized area. Therefore, DA16200 provides bus protection for serial slave interfaces.

The features of bus protection in DA16200 are summarized as follows:

■ Up to two accessible areas can be set and the setting unit is 4-byte

■ The bus protection provides the write/read protection function outside the set area

For more information to use this function, see Ref. [2].

7.10 Watchdog Timer

The watchdog timer in DA16200 is based on a 32-bit down-counter that is initialized from the reload

the programmed value. The counter decrements by one on each positive clock edge of WDOGCLK

when the clock enable, WDOGCLKEN, is HIGH.

The watchdog monitors the interrupt and asserts a reset request signal, WDOGRES, when the

counter reaches 0, and the counter is stopped. On the next enabled WDOGCLK clock edge, the

counter is reloaded from the WDOGLOAD register and the countdown sequence continues. If the

interrupt is not cleared by the time the counter reaches 0 for a second time, the watchdog timer

reasserts the reset signal.

The watchdog timer applies a reset to the system in the event of a software failure, providing a way

to recover from software crashes. The watchdog unit can be enabled or disabled as required.

Figure 20 shows the watchdog timer block diagram.

Figure 20: Watchdog Timer Block Diagram

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