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DA16200 датащи(PDF) 64 Page - Renesas Technology Corp

номер детали DA16200
подробное описание детали  Ultra Low Power Wi-Fi SoC
PDF  154 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA16200 датащи(HTML) 64 Page - Renesas Technology Corp

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DA16200
Ultra Low Power Wi-Fi SoC
Datasheet
Revision 3.6
04-Jan-2023
CFR0011-120-00
64 of 153
© 2023 Renesas Electronics
9.7.2
I2S Clock Scheme
The I2S uses a 24 MHz clock as default from the RF reference clock (40 MHz), so it can support
46.875 KHz of sampling rate. External clock sources are needed to support the standard sampling
rate. See Table 49.
Figure 39: I2S Clock Scheme
Table 49: I2S Clock Selection Guide
Parameter
Units
LRCK
Fs
8
12
16
24
32
44.1
46.875
48
KHz
BCLK
64Fs
0.512
0.768
1.024
1.536
2.048
2.8224
3
3.072
MHz
MCLK
512Fs
4.096
6.144
8.192
12.288
16.384
22.5792
24
24.576
MHz
Clk Div2
N
(=1,2,3…)
6
4
3
2
2
1
1
1
I2S_CLK
24.576
24.576
24.576
24.576
32.768
22.5792
24
(Internal
PLL)
24.576
MHz
NOTE
To confirm the exact LRCK operation, drive the Clock source at I2S_CLK.



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