DA16200 datasheet(44/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

44 of 153

● IDLE: waits for the DMA request. When the DMA request appears, the state moves to R_FIRST

● R_FIRST: reads the address of the first DMA descriptor (head node of the linked list)

● R_COMMAND: reads the Command Field of the DMA descriptor

● R_SRC_ADDR: reads the Src_start_addr Field of the DMA descriptor

● R_DST_ADDR: reads the Dst_start_addr Field of the DMA descriptor

● R_DATA: reads the data from the source address

● W_DATA: writes the data read in the R_DATA state to the destination address. By the

information written in the DMA descriptor, if data read/write is required, the state moves to

R_DATA. If the DMA task is required to be suspended or stopped, the state moves to

W_COMMAND

● R_NEXT: reads the next_descriptor field to check whether the next DMA task exists or not,

before stopping the current DMA task

● W_FIRST: writes the address of the next DMA descriptor read in R_NEXT to the memory region

where the first address of the DMA descriptor is stored. If arbitration is required, the state moves

to IDLE state. If the current DMA channel is required to be operated, the state moves to R_FIRST

state

● INIT, R_FIRST_LOAD, R_NEXT_LOAD, and C_NEXT: reduce the critical path delay in the DMA

block. These states generate one clock delay

7.7.2

DMA2 (Fast DMA)

DMA2 (Fast DMA) controller consists of a master read port, a master write port, and a slave port for

configuration register setting. Fast DMA performs bulk data transfers, data reading from the source

address range, and data writing to the destination address range. Fast DMA is mainly used for fast

data transfer from memory to memory.

The features of Fast DMA in DA16200 are summarized as follows:

■ Transfer size is programmable from 1 byte to 1 Megabytes

■ Up to four channels can be set at the same time

■ LLI function of ring type is supported by using configuration registers of four channels

■ Interrupt enable can be set for each channel

■ Provides a hold function to pause data transfer for each channel

The basic unit of bus transmission is 32-bit and has a function to automatically correct address align,

even if the source and destination addresses are not in word units.

For example, assuming that the transfer size is 23 bytes, the source base address is 0x001 for read

access, and the destination base address is 0x102 for write access, the number of bytes per

transaction is performed as follows:

● Source base address [1:0] = 0x1: the master read port of fast DMA performs read access with the

following sequences:

○ 1 -> 2 -> 4 -> 4 -> 4 -> 4 -> 4 bytes

● Destination base address [1:0] = 0x2: the master write port of fast DMA performs write access

with the following sequences:

○ 2 -> 4 -> 4 -> 4 -> 4 -> 4 -> 1 bytes

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