DA16200 datasheet(40/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

40 of 153

7.5

Pulse Counter

7.5.1

Introduction

The pulse counter is a module that counts the number of rising or falling edges of input signals. And

this counter module can run even in Sleep mode 2/3. It includes one 32-bit up-counter. The input

channel can be set with a register setting among the 11 digital I/Os. It also has a glitch filter that is

designed to remove the unwanted trigger of an input signal.

7.5.2

Functional Description

Ext.

Pad

Mux.

Mux_SEL

Glitch

Filter

Edge

Select

Counter

Int

Gli_En

Gli_Thresh

Edge_Sel

Count_En

Count_Rst

Int_Clr

Int_Thresh

Int

PCLK

Pulse

Edge

Pulse

Count

CLK_32kHz

ㅣ

Figure 16: Pulse Counter Block Diagram

7.5.2.1

Input

Available input channels are described in Table 29. It uses the same input sources with the wake-up

controller. By register setting, input channels can be selected among 11 digital I/Os.

7.5.2.2

Clock

The operation clock of the pulse counter is 32 kHz.

7.5.2.3

Counter

As described in Figure 16, the pulse counter is activated by several counter control signals. With a

the glitch filter module, the Gli_En and Gli_Thresh register values need to be set. The pulses whose

cycles are shorter than the Gli_Thresh value are removed. The counter is a 32-bit up-counter and the

counter value can be reset to zero by Count_Rst.

7.5.2.4

Interrupts

An interrupt occurs when the counter values reaches the Interrupt Threshold value (Int_Thresh). In

Sleep mode 2/3, this interrupt can be used as a wake-up source.

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