DA16200 datasheet(98/154 Pages) RENESAS

98 / 154 page

DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

98 of 153

Table 137: UART_LCNTRL (0x02C)

Bit

Mode

Symbol

Description

Reset

15:8

Reserved

0x00

R/W

SPS

Stick parity select

0 = Stick parity disabled

1 = Either

* If PARSEL bit is 0, the parity bit is transmitted and

checked as a 1

* If PARSEL bit is 1, the parity bit is transmitted and

checked as a 0

0x0

6:5

R/W

DTLEN

The number of data bits transmitted or received in a

frame.

b'11 = 8 bits

b'10 = 7 bits

b'01 = 6 bits

b'00 = 5 bits

0x0

R/W

FIFOEn

FIFO Enable

0 = UART FIFO disabled

1 = UART Transmit and Receive FIFO enabled

0x0

R/W

TSTP

Two stop bits select

0 = Two bits are transmitted as stop bit

1 = One bit is transmitted as stop bit

0x0

R/W

PARSEL

Parity select:

0 = odd parity

1 = even parity

0x0

R/W

PAREn

Parity enable:

0 = Parity is disabled

1 = Parity is enabled

0x0

Reserved

0x0

Table 138: UART_CNTRL (0x030)

Bit

Mode

Symbol

Description

Reset

R/W

CTSEn

UART CTS hardware flow control enable

0 = CTS hardware flow control disabled

1 = CTS hardware flow control enabled

0x0

R/W

RTSEn

UART RTS hardware flow control enable

0 = RTS hardware flow control disabled

1 = RTS hardware flow control enabled

0x0

13:10

Reserved

0x0

R/W

RXEn

Receive enable

0 = Receive section of the UART disabled

1 = Receive section of the UART enabled

0x1

R/W

TXEn

Transmit enable

0 = Transmit section of the UART disabled

1 = Transmit section of the UART enabled

0x1

DA16200 датащи(PDF) 98 Page - Renesas Technology Corp

DA16200 датащи(HTML) 98 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL