DA16200 datasheet(114/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

114 of 153

Table 163: HIF_PAD_CTRL (0x5003_0020)

Bit

Mode

Symbol

Description

Reset

31:30

Reserved

29:28

R/W

HCOE_DLY

Output Enable Delay Control for Host Command signal

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

27:26

R/W

HCO_DLY

Output Delay Control for Host Command signal

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

25:24

R/W

HCI_DLY

Input Delay Control for Host Command signal

00: No delay

01: 1-unit delay

10: 2-unit delay

11: 3-unit delay

2'b00

23:22

R/W

HDATI_ST

Input Schmitt Trigger Level Control for Host Data signals

2'b00

21:20

R/W

HDAT_PUD

Host Data signals Pull-Up/Down Control

00: No Pull-Up/Down

01: Pull-Down

10: Pull-Up

11: Keeper

2'b00

19:16

R/W

HDATO_DS

Output Drive Strength Control for Host Data Signals

2'b00

15:14

R/W

HCMDI_ST

Input Schmitt Trigger Level Control for Host Data signals

2'b00

13:12

R/W

HDAT_PUD

Host Command signals Pull-Up/Down Control

00: No Pull-Up/Down

01: Pull-Down

10: Pull-Up

11: Keeper

2'b00

11:8

R/W

HCMDO_DS

Output Drive Strength Control for Host Command Signals

4'h0

7:6

Reserved

5:4

R/W

HCLK_PUDC

Host Clock signals Pull-Up/Down Control

00: No Pull-Up/Down

01: Pull-Down

10: Pull-Up

11: Keeper

2'b00

3:0

R/W

HCLK_DS

Host Clock Control Count Register

Output Drive Strength Control for Host Clock Signals

4'h0

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