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DA16200 датащи(PDF) 112 Page - Renesas Technology Corp |
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DA16200 датащи(HTML) 112 Page - Renesas Technology Corp |
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112 / 154 page ![]() DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 112 of 153 © 2023 Renesas Electronics Table 160: HIF_CMD_IDX (0x5003_0014) Bit Mode Symbol Description Reset 31:16 - - Reserved 15 R/W CMDQ_TRIG Trigger to transfer the value of Command Index and Argument registers into Command Index Queue and Command Argument Queue registers. The trigger (transfer) operation is only active when the value of this bit is high, and the status of command queue is not busy (QBUSY_ST) 1'b0 14 R/W CMD_TCTL Command Trigger Control 0: Start a new command immediately when the command trigger (CMDQ_TRIG) bit was set 1: Only start a new command when the command trigger (CMDQ_TRIG) bit was set and the previous response result has been read 1'b0 13 R/W STB_CTL Command Start Bit and Transmission Bit Control 0: The start bit and transmission bit of the SD/eMMC command is automatically generated by H/W circuit 1: The start bit and transmission bit of the SD/eMMC command refers to the STR_BIT and TRM_BIT of this control register 1'b0 12:11 R/W RSP_TYPE Response Type Control 00: No Response 01: R3 Response 10: Short Response (Total: 48 bits) 11: Long Response (Total: 136 bits) 2'b00 10:9 R/W DATA_TYPE Data Type Control 0x: Command only (without data transfer) 10: Command with single/multiple read data 11: Command with single/multiple write data 2'b00 8 - - Reserved 7 R/W STR_NIT This register specifies the value of the start bit of SD/eMMC command if STB_CTL bit is set to high. Otherwise, it is not used 1'b0 6 R/W TRM_BIT This register specifies the value of the transmission bit of SD/eMMC command if STB_CTL bit is set to high. Otherwise, it is not used 1'b1 5:0 R/W HIF_CMD_IDX This register specifies the value of the SD/eMMC command index 6'h0 Table 161: HIF_CMD_ARGQ (0x5003_0018) Bit Mode Symbol Description Reset 31:0 R HCLK_CMD_ARG This register is a queue to receive the value of the SD/eMMC command argument register when the trigger (transfer) operation is active 32'h0 |
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