DA16200 datasheet(52/154 Pages) RENESAS

номер детали	DA16200

подробное описание детали	Ultra Low Power Wi-Fi SoC

PDF	154 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

52 of 153

9.2

SPI Master

QSPI can use the SPI master with the use of a single line interface. Table 34 shows the pin definition

of the SPI master interface. SPI signal timing is the same as QSPI.

To use DA16200 as an SPI master, the CSB signal can be used with any of the GPIO pins. CSB [3:1]

can be selected from the GPIO special function by setting the registers in the GPIO.

Table 34: SPI Master Pin Configuration

Pin Name

Pin Number

I/O

Function Name

QFN

fcCSP

GPIOx

E_SPI_CSB[3:1]

GPIOA6

E_SPI_CSB[0]

GPIOA7

E_SPI_CLK

GPIOA8

I/O

E_SPI_MOSI or E_SPI_D[0]

GPIOA9

I/O

E_SPI_MISO or E_SPI_D[1]

GPIOA10

I/O

E_SPI_D[2]

GPIOA11

I/O

E_SPI_D[3]

E_SPI_CSB

E_SPI_CLK

E_SPI_D[3:0]

TCLK.ON

TDO.DLY

TDI.SU

TCSB.OF

Figure 25: SPI Master Timing Diagram (Mode 0)

Table 35: SPI Master Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

QSPI_CLK frequency

FCLK

MHz

QSPI_CLK clock duty

1st CLK active rising transition time

TCLK.ON

0.5 × TCLK

TCLK

(Note 1)

QSPI_CSB non-active rising transition time

TCSB.OFF

TCLK

QSPI_D[3:0] input setup time

TDI.SU

QSPI_D[3:0] output delay time

TDO.DLY

Note 1

TCLK = (FCLK× 106)-1 seconds.

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